Positive-Edge-Triggered JK flip-flops

  • Thread starter Lanot
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In summary, the conversation discusses the use of Positive-Edge-Triggered JK flip flops in a circuit simulation and the search for a simpler version of the flip-flop to speed up the process. The conversation also mentions alternative flip-flop designs and technologies, such as D flip-flops and different CMOS technologies. Ultimately, the focus is on finding a flip-flop design with a lower number of transistors for faster simulation.
  • #1
Lanot
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Hi guys,

I'm simulating a circuit which uses a few (actually, 10) Positive-Edge-Triggered JK flip flops.

The exact flip-flop design that I'm using is the SN7476 from TI. I need a flip-flop like this, since I need Preset and Clear asynchronous inputs. The datasheet is as follows:
http://www.ti.com/lit/ds/symlink/sn7476.pdf

In fact, as I'm simulating a circuit with MOS only transistors, I found an adaptation for this circuit on the following link:
http://tams-www.informatik.uni-hamb...16-flipflops/40-jkff/SN7476-single_print.html which simplifies my circuit a little bit.

As I use it for simulation, I'd like to use a simpler version of this flip-flop, to speed up the process (at this moment, my focus is not the design, I just need to make things faster.)

Is there an alternative for this circuit which uses a lower number of transistors?
I know this is an Master/Slave flip-flop. I tried to inplement an equivalent circuit using this topology: http://2.bp.blogspot.com/-fxhp4O9oDEo/UGH4G6SSF8I/AAAAAAAAAJ0/ueUKXx0-Eew/s1600/jkffcirc.gif as well as this one http://wearcam.org/ece385/lectureflipflops/flipflops/fig6a.gif with the additional preset/clear signals, but it didn't work as expected.

Is there any equivalent popular IC to SN7476? I know that SN7476 is "obsolete", so I took a look at NXP's 74LVC109, but the number of gates goes beyond what I need right now.

Any ideas?
Thank you in advance.
 
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  • #2
Is there a reason you're using JK flip-flops? You can do anything with a D flip-flop and it is much simpler.
 
  • #3
Not sure why you chose JK. Not sure how fast you want to go. There are lots of 7474 equivalent D flops with set and reset on each flop.

High Speed CMOS 74AC74 (125MHz @ 5V)

There are different technologies, like ECL and SIGe that go to the GHz.
 
  • #4
analogdesign said:
Is there a reason you're using JK flip-flops? You can do anything with a D flip-flop and it is much simpler.
It's an old design for a control logic of an ADC. It was proposed on 1972. They proposed a version using D flip flops, which uses 2N+2 DFFs and a version with JK with N+1 FFs. Of course it was targeted to LSI/MSI applications.

I did some calculations, and found out that the JK version requires 540 transistors (using the 7476 topology), while the D version requires 648 (using 7474). My simulations show that, because of this, the JK version is much faster.
These simulations take a lot of time. My goal right now is to speed up the process a little bit more...

The point is: I don't care exactly about the flip-flop type right now, but the number of transistors they use...

Thank you.
 
  • #5
meBigGuy said:
Not sure why you chose JK. Not sure how fast you want to go. There are lots of 7474 equivalent D flops with set and reset on each flop.

High Speed CMOS 74AC74 (125MHz @ 5V)

There are different technologies, like ECL and SIGe that go to the GHz.

Like I said before (in other words), the good old 7474 ( http://home.gwi.net/~pstewart/7474diag.gif ) uses 6 nand3 gates (which in cmos would require 36 transistors).

For the design I'm using, despite the higher number of transistors/flip-flop, it's still a better trade-off in terms of transistor count.

But thank you for your suggestion.
 
  • #6
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  • #7
meBigGuy said:
You are building a custom asic? You are going to build custom flops? What technology are you working in?

It is hard for me to understand why a JK design would require 1/2 the flops of a D design.

Not building exactly, just designing. I'm free to use custom flip-flops. I just used the ones that the paper suggested.

Take a look at: http://ipnpr.jpl.nasa.gov/progress_report2/XIII/XIIIW.PDF
p. 5 shows the classical approach with D flip flops and p. 9 shows the alternative one with JK FFs
 
  • #8
I added a link to my previous post while you were replying.

http://electronics.stackexchange.com...e-of-the-clock shows a 10 transistor d-flop
 
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  • #9
BTW, You can add transistors (logic) to the basic 10 transistor D flop to get JK functionality. I'll let you play with that.
 
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FAQ: Positive-Edge-Triggered JK flip-flops

1. What is a positive-edge-triggered JK flip-flop?

A positive-edge-triggered JK flip-flop is a sequential logic circuit that stores and outputs a single bit of information. It is triggered by a rising edge of a clock signal, and the output changes only when the clock signal is at a high level.

2. How does a positive-edge-triggered JK flip-flop work?

The JK flip-flop has two inputs: J and K. When both inputs are set to 0, the output remains unchanged. When J=1 and K=0, the output Q becomes 1. When J=0 and K=1, the output Q becomes 0. When both inputs are set to 1, the output toggles, meaning it changes from 0 to 1 or from 1 to 0 depending on its previous state.

3. What are the advantages of using positive-edge-triggered JK flip-flops?

Positive-edge-triggered JK flip-flops have a simpler design compared to other types of flip-flops, making them easier to implement. They also have a more stable output due to the use of a clock signal, which reduces the risk of glitches and errors in the output.

4. How are positive-edge-triggered JK flip-flops used in practical applications?

Positive-edge-triggered JK flip-flops are commonly used in digital systems for storing and transferring data. They are also used in counters and frequency dividers, as well as in memory elements such as registers and shift registers.

5. What are the limitations of positive-edge-triggered JK flip-flops?

One limitation of positive-edge-triggered JK flip-flops is that they can only be triggered by a rising edge of a clock signal. This means that they cannot be used in asynchronous circuits where the inputs can change at any time. They also require a stable and consistent clock signal for proper operation.

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