VHDL Code: Testing Equality of Vectors

In summary, the conversation discusses code for checking if certain 8 bit and 4 bit vectors are equal to specific values, and the error that the speaker is receiving while trying to implement this code. They mention that the code is inside a process and request help in finding the issue.
  • #1
user101
207
0
Hi all, I have the following code:

if (checkHR(7 downto 4) = HRH) and (checkHR(3 downto 0) = HRL)
and (checkMIN(7 downto 4) = MINH) and (checkMIN(3 downto 0) = MINL) then

SECL <= "0000";
SECH <= "0000";
MINL <= "1000"; -- set to 8888 to notify alarm has been set
MINH <= "1000"; -- set to 8888 to notify alarm has been set
HRL <= "1000"; -- set to 8888 to notify alarm has been set
HRH <= "1000"; -- set to 8888 to notify alarm has been set

where checkHR and checkMIN are 8 bit vectors (7 downto 0)... and SECL, SECH, MINL, MINH, HRL, and HRH are all 4 bit vectors (3 downto 0).

What I'm trying to do is check to see if the first four bits of checkHR is equal to HRH.

Can someone tell me what's wrong? I'm getting the error: Line 74. = can not have such operands in this context.
 
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  • #2
Did you put the code inside a process? You can only use the "if" statement inside a process.
 
  • #3
Yes, it's in a process.
 
  • #4
In the portion of code that you posted there is no syntax error. There must be some conflicting code somewhere else. You should post the whole process. Also tell us which of SECL, SECH, MINL, MINH, HRL, HRH, checkHR and checkMIN, are signals and which are ports.
 

Related to VHDL Code: Testing Equality of Vectors

1. What is VHDL code used for in testing equality of vectors?

VHDL (VHSIC Hardware Description Language) is a programming language commonly used in the design and simulation of digital electronic systems. In this context, it can be used to write code that tests the equality of vectors, which are data structures that contain multiple elements.

2. How does VHDL code test for equality of vectors?

VHDL code uses logical operators and conditional statements to compare the elements of two vectors and determine if they are equal. The code can also be written to check for equality of vectors of different sizes by padding or truncating the vectors as needed.

3. What are the advantages of using VHDL code for testing equality of vectors?

VHDL code allows for efficient and accurate testing of equality of vectors, as it is specifically designed for working with digital systems. It also allows for easy modification and debugging of the code, making it a versatile tool for testing and verifying vector equality.

4. Are there any limitations to using VHDL code for testing equality of vectors?

One limitation of using VHDL code for testing vector equality is that it may require a strong understanding of the language and digital systems design, making it less accessible to those without this background. Additionally, the code may need to be modified for different hardware platforms.

5. Can VHDL code be used for testing equality of vectors in real-time systems?

Yes, VHDL code can be used for testing vector equality in real-time systems. However, it is important to ensure that the code is optimized for speed and efficiency in order to accurately test the vectors in real-time. This may require additional knowledge and expertise in VHDL programming.

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