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VHDL Code: Testing Equality of Vectors |
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| Dec1-07, 11:21 PM | #1 |
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VHDL Code: Testing Equality of Vectors
Hi all, I have the following code:
What I'm trying to do is check to see if the first four bits of checkHR is equal to HRH. Can someone tell me whats wrong? I'm getting the error: Line 74. = can not have such operands in this context. |
| Dec2-07, 04:29 PM | #2 |
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Did you put the code inside a process? You can only use the "if" statement inside a process.
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| Dec2-07, 10:56 PM | #3 |
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Yes, it's in a process.
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| Dec3-07, 03:27 PM | #4 |
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VHDL Code: Testing Equality of Vectors
In the portion of code that you posted there is no syntax error. There must be some conflicting code somewhere else. You should post the whole process. Also tell us which of SECL, SECH, MINL, MINH, HRL, HRH, checkHR and checkMIN, are signals and which are ports.
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