Hexadecimal number on seven-segment

[dawnoflife]

I need to design a bank of four 4-bit registers whose contents are displayed on the seven-segment displays. So, basically just display 4 hexadecimal numbers on the 7-segment. The output switches on its own with every clock cycle. I'm using a Basys2 board for this. This is what I have so far...

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Register_Bank is
port( x: in std_logic_vector(3 downto 0);
        disp_en: out std_logic_vector(3 downto 0);
        z:  out std_logic_vector(7 downto 0);
        ck,reset: in std_logic);
end Register_Bank;

architecture Behavioral of Register_Bank is

Type my_state is(s0,s1,s2,s3);
Signal n_s: my_state;
Signal ck_div: std_logic;
Signal temp,temp1,temp2,temp3,temp0,temp_main: std_logic_vector(0 to 3);
Signal R0,R1,R2,R3 : std_logic_vector(3 downto 0);

begin

-- 
process(temp_main)
begin
case temp_main is
    when "0000" => z <= "00000011";
    when "0001" => z <= "10011111";
    when "0010" => z <= "00100101";
    when "0011" => z <= "00001101";
    when "0100" => z <= "10011001";
    when "0101" => z <= "01001001";
    when "0110" => z <= "01000001";
    when "0111" => z <= "00011111";
    when "1000" => z <= "00000001";
    when "1001" => z <= "00001001";
    when "1010" => z <= "00010001";
    when "1011" => z <= "11000001";
    when "1100" => z <= "01100011";
    when "1101" => z <= "10000101";
    when "1110" => z <= "01100001";
    when "1111" => z <= "01110001";
    when others => null;

--temp3 <= x<3>;
--temp2 <= x<2>;
--temp1 <= x<1>;
--temp0 <= x<0>;

--wiring the register contents to outputs
temp3 <= R3;
temp2 <= R2;
temp1 <= R1;
temp0 <= R0;

--state machine for TMD
Process(x,ck_div)
begin
if ck_div ='1' and ck_div'event then
case n_s is
    when s0 => 
        temp <= x<0>; 
        disp_en <= "0111";
        n_s <= s1;
    when s1 =>
        temp <= x<1>;
        disp_en <= "1011";
        n_s <= s2;
    when s2 =>
        temp <= x<2>;
        disp_en <= "1101";
        n_s <= s3;
    when s3 =>
        temp <= x<3>;
        disp_en <= "1110";
        n_s <= s0;  
end case;
end if;
end process;

-- clock division
process(ck)
variable count: integer;
begin
if ck ='1' and ck'event then
    if reset ='1' then
        count := 0;
        ck_div <= '0';
    elsif reset ='0' then
        if count = 999999 then
            ck_div <= not ck_div;
            count := 0;
        else
            count := count + 1;
        end if; 
    end if;
end if;
end process;    

end Behavioral;

I know the logic is off and there are syntactical errors as well. I need help trying to debug this. I'd greatly appreciate help!

 

[KataKoniK]

Hi there,

I can offer some suggestions to help you create a functional design for your bank of four 4-bit registers.

Firstly, it's important to define the purpose of your design and the desired behavior. From your post, it seems like you want to display 4 hexadecimal numbers on the seven-segment displays, with the output switching automatically with every clock cycle. Is there a specific sequence or pattern that you want the numbers to follow? This will help guide your design decisions.

Next, let's take a look at your code. It's great that you have defined your entity and ports, but there are some issues with your architecture.

1. Missing "begin" and "end" statements: In your architecture, you have defined a process for temp_main and another process for x and ck_div, but you have not included the necessary "begin" and "end" statements. These statements are important as they define the beginning and end of a process.

2. Incomplete case statement: In your temp_main process, you have a case statement but it is missing the "when others" case. This case is needed to handle any inputs that do not match the specified cases. In this case, you can simply assign z to "00000000" for any other input.

3. Incorrect use of signals: In your temp_main process, you have defined temp3, temp2, temp1, and temp0 as signals, but you are assigning them to the outputs of your registers (R3, R2, R1, and R0). Signals are used to transfer values between processes, but in this case, you should use variables instead.

4. Incomplete process: In your main process, you have defined a case statement for n_s, but you are not actually using the values of n_s in your code. In addition, you have not included a clock in your sensitivity list, which means that the process will not be triggered by any clock events.

5. Clock division: Your clock division process seems to be missing a "begin" statement as well. In addition, it may be easier to use a counter variable instead of a variable to keep track of the clock cycles.

6. Missing reset condition: In your main process, you have not included a condition for the reset signal. This is important as it will allow your design to reset to a known state before starting its normal operation.

In addition to these issues, there may