Even and odd parity detector with active high/low inputs

In summary, the task is to build a 3-bit active-low odd-parity detector using a single 74x138 chip. The output, labeled "P", will be logic 0 when an odd number of inputs are logic 1. This can be achieved using a NAND gate and a NOR gate with arbitrary fan-in.
  • #1
thrainbow
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Homework Statement


Using a single 74x138, build a 3-bit, active-low, odd-parity detector. (Y0-Y7 are selected by "b2 b1 b0" in binary. Also the nibble "0 0 0" is considered even parity) You may use one NOR gate and one NAND gate, with arbitrary fan-in(>1). Label input variables "I2 I1 I0" and output variables "P".

Homework Equations


I'm just very confused about the fact that it's active low and odd parity. Does that mean the output will be a 1 for all of the inputs that have an odd number of 0's? What would happen if it was active low/even parity, active high/even parity, or active high/odd parity? Please help me to understand.

The Attempt at a Solution


I am thinking that I need to look for all inputs that have an odd number of 0's and the output P will be a 1. But I am not entirely sure about the answer. Also, to connect all of the outputs to a NAND gate and then to a NOR gate?
 
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  • #2
thrainbow said:
active-low, odd-parity detector
thrainbow said:
Does that mean the output will be a 1 for all of the inputs that have an odd number of 0's?

No this just refers to the output pin. Break that down...

It's an "odd-parity detector" so the output will be ACTIVE when an odd number of inputs are logic 1.
The output is "active-low" which means the output will be logic 0 when ACTIVE.
So all together..
The output will be Logic 0 when an odd number of inputs are logic 1.

If the output had been described as "active-high" then the output would have been logic 1 with an odd number of logic 1's present.
 

1. What is an even and odd parity detector with active high/low inputs?

An even and odd parity detector with active high/low inputs is a circuit that is used to check whether the number of bits in a binary data stream is even or odd. It receives a binary input and produces a high or low output depending on whether the number of 1s in the input is even or odd.

2. How does an even and odd parity detector with active high/low inputs work?

The circuit consists of an XOR gate and a flip-flop. The input is connected to both the XOR gate and the flip-flop. The XOR gate compares the input with the previous output of the flip-flop. If the input has an odd number of 1s, the XOR gate will produce a high output, which will be stored in the flip-flop. If the input has an even number of 1s, the XOR gate will produce a low output, which will be stored in the flip-flop. The output of the flip-flop indicates whether the input has an even or odd number of 1s.

3. What are the advantages of using an even and odd parity detector with active high/low inputs?

One advantage is that it can detect single-bit errors in the input data. If a single bit is flipped during transmission, the output of the circuit will change, indicating an error. Another advantage is that it is simple and easy to implement.

4. What are the applications of an even and odd parity detector with active high/low inputs?

This circuit is commonly used in communication systems to detect and correct errors in transmitted data. It is also used in memory systems to ensure data integrity.

5. Can an even and odd parity detector with active high/low inputs detect multiple-bit errors?

No, this circuit can only detect single-bit errors. If multiple bits are flipped during transmission, the output of the circuit will still indicate that the number of 1s is either even or odd, and the error will go undetected.

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