Implementation of ALU using Verilog

[PainterGuy]

Hi,

I'm trying to learn Verilog and was exploring different ways to write a simple Verilog code for Arithmetic Logic Unit, ALU. I was going through this webpage: https://esrd2014.blogspot.com/p/8-bit-arithmetic-and-logic-unit.html

I'm just curious to know that why they are using 16 bit output register' please see the capture below taken from the mentioned webpage. They could have simply used 9 bit register instead. Is the reason being that the registers come in standard sizes such 8-bit, 16-bit, 32-bit, etc.?

Actually, I'm planning to modify the given code to come up with a simple ALU code but I thought to confirm about the 16-bit output register first. Thanks for the help, in advance!

 

[Baluncore]

I'm just curious to know that why they are using 16 bit output register'

Because an 8x8 bit multiply doubles the number of bits, to 16 in the result.

 

[PainterGuy]

Because an 8x8 bit multiply doubles the number of bits, to 16 in the result.

Sorry, I missed to see that it was also doing multiplication. I think the reason being that the ALU I was thinking of was a simple addition and subtraction one. I'll attempt the code tomorrow.

Thanks for pointing this out.

 

[PainterGuy]

Hi again,

I tried to write simple code for an ALU. I'm sure there would be different ways to do it but I chose which made sense to me.

I'm sure there would be many errors but the ones I'm presently encountering are highlighted below; lines 31 and 32.

Sorry about the bad indentation.

Could you please help me to fix it? Thank you, in advance!

module ALU(
           ALU_Out,
           A,B,ALU_Sel             
    );
  
    parameter N = 4;
  
    input wire [N-1:0] A,B;
    input wire [1:0] ALU_Sel;
    output reg [N-1:0] ALU_Out;
  
  
    parameter [1:0] ADD     = 2'b00,
                    SUB     = 2'b01,
                    B_AND    = 2'b10,
                    B_OR    = 2'b11;
    
    reg overflow_flag, sign_flag, zero_flag;
 
 
 
    always @(ALU_Sel or A or B)
        begin

        case(ALU_Sel)
            ADD:
               ALU_Out = A + B ;
            
            SUB:
                  begin
                  assign B = ~B + 1 ; // 2's complement
                  ALU_Out = A + B;
                  end
                
            B_AND:
               ALU_Out = A & B;
            
            B_OR:
               ALU_Out = A | B;
          
            default: ALU_Out = A + B ;
        endcase
      
  
    assign c_in = {1'b0,A[N-2]} + {1'b0,B[N-2]};
    assign c_out = {1'b0,A[N-1]} + {1'b0,B[N-1]};
  
    if (c_in==c_out)
        overflow_flag = 0;
    else
        overflow_flag = 1;
      
  
    if (ALU_Out[N-1] == 1)
        sign_flag = 1;
    else
        sign_flag = 0;
      
  
    if (ALU_out == 0)
         zero_flag = 1;
    else
         zero_flag = 0;
      
    end

endmodule

 

[Baluncore]

It will be necessary to analyse every line to check exactly what it does.
Do you have a link to the appropriate Verilog syntax reference ?

 

[PainterGuy]

Do you have a link to the appropriate Verilog syntax reference ?

I'm learning it using different webpages and YouTube videos.

Could you please help me with fixing the Verilog syntax?

 

[Baluncore]

Could you please help me with fixing the Verilog syntax?

Verilog is not like creative writing. It must be precise and correct.
You need to engineer an exact and correct solution.
To succeed you need to be fixative and obsessive.
Any attempt to bounce of the error messages will end with unreliable garbage.
I would start with the syntax documentation for the software being used.
Without the syntax definition, all is lost.

 

[Baluncore]

Computer Arithmetic and Verilog HDL Fundamentals -2010- Joseph Cavanagh

Complement ...
In C; ~X
In Verilog 'X

 

[PainterGuy]

Computer Arithmetic and Verilog HDL Fundamentals -2010- Joseph Cavanagh

Complement ...
In C; ~X
In Verilog 'X

Thank you for the recommendation.

I'm sorry but I don't think what I did to find 2's complement was wrong. I'm inverting the bits of B and then adding 1 to get 2's complement. Could you please give it look?

B = ~B + 1'b1 ; // 2's complement

 

[Baluncore]

Could you please give it look?

Not without the syntax reference for the system you are using.

 

[PainterGuy]

Not without the syntax reference for the system you are using.

I'm sorry but I'm not following you. I'm trying to use Verilog. You want me to send you a reference which shows how Verilog syntax works? Thanks!

 

[Baluncore]

I'm sorry but I'm not following you. I'm trying to use Verilog. You want me to send you a reference which shows how Verilog syntax works? Thanks!

No, I want you to find a reference and give me a link.

It is 30 years since I have needed to use VHDL in anger. If you want me to get back into that mindset, then I will need a language reference compatible with the software you are using that produces the error messages. What is that software ?

 

[PainterGuy]

No, I want you to find a reference and give me a link.

It is 30 years since I have needed to use VHDL in anger. If you want me to get back into that mindset, then I will need a language reference compatible with the software you are using that produces the error messages. What is that software ?

I'm sorry that I didn't reply to you earlier. Sure, I'll do it. If you don't mind, I will be sending you a PM. Thank you!