- #1
reddvoid
- 119
- 1
Hi,
I have a post layout extracted netlist, In which I am interested in input capacitance on clock pin,
If i measure clock pin input capacitance on post layout extracted netlist, I am getting 1.58fF
and when I measure the same in schematic, I am getting 0.6fF
and I am able to find the paracitics in the clock pin to be 0.4fF (from .spf file)
so the schematic cap + Parasitic cap. should add up to post layout cap right ?
I am not able to trace where the remaining 0.58fF coming from in post layout cap.
I have a post layout extracted netlist, In which I am interested in input capacitance on clock pin,
If i measure clock pin input capacitance on post layout extracted netlist, I am getting 1.58fF
and when I measure the same in schematic, I am getting 0.6fF
and I am able to find the paracitics in the clock pin to be 0.4fF (from .spf file)
so the schematic cap + Parasitic cap. should add up to post layout cap right ?
I am not able to trace where the remaining 0.58fF coming from in post layout cap.