Lab Memo: Flip-Flop Analysis - 4 bit counter

[ravenprp]

Hi, I have a four-bit binary counter utilizing two 74LS76 and two 74LS74 integrated circuits. I've attached a picture.

I have to write a lab report, and this is what I have so far:


If we were to label each flip-flop from 1 to 4 (left to right) in Figure 3B, Appendix B, each successive output is halved. Assume f0 is the original clock pulse.
o The general equation for the frequency yields: fN = f0 / 2N where N is the number of the respective flip-flop in sequence.
 The output of flip-flop #1: f0 / 2
 The output of flip-flop #2: f0 / 4
 The output of flip-flop #3: f0 / 8
 The output of flip-flop #4: f0 / 16


Disregard the Appendix refernece. Is this correct?



EDIT -- added the picture, I forgot

 

[berkeman]

Looks okay to me, within the limitations of ripple counters. Quiz question -- what's the difference between a ripple counter and a synchronous counter. When would you not want to use a ripple counter?

 

[ravenprp]

Oh, I know this. Ripple counter -- is asynchronous because its not controlled by a common clock, rather the flip flops are cascaded so they take in CP from the previous Q. Syncrhonous is a common clock.

Plus you have propogation delays with ripple counters.

f = 1 / N * t_prop