Multiplexer Definition and 22 Threads

I(0)=0, so 0 and 1 are not minterms. I(1)=1, so 2 and 3 are minterms. I(2)=D, so 5 is a minterm but 4 is not a minterm. I(3) not sure I(4) not sure I(5) not sure I(6)=1⊕0=1, so 12 and 13 are also minterms. I(7)=1⊕1=0, so 14 and 15 are not minterms. I don't know how to deal with the rest of...

Hi everyone, I've been trying to design a 12:1 2.0 USB multiplexer for a while, with very little success. I've bought a couple of MAX4999 8:1 multiplexers, trying to use two of them in parallel such as shown in the datasheet. I've put them on a breakout board from Adafruit, and started testing...

First let me just I'm a total newbie to electronics, but I would like to progressively learn how computers work by building the little components with the small parts, and then work up to the ICs once I understand how to make rudimentary versions. I'm trying to make a 1-bit multiplexer out of...

Purpose: Create a position sensor using LEDs. Goal: Increase or decrease a pulse width in response to direction of movement. Chips Involved: 1) Clock. 2) 2x DM74150 (16×1 Multiplexers.) 3) 2x SN74193 (4-bit Binary Counters.) 4) 1x SN74LS112 (Negative Edge Master Slave JK Flip-Flop.) 5) 1x...

Homework Statement Design a component that uses a 4-to-1 multiplexer to choose between one of four different operations to get the result from. Each of the operations and the multiplexer should be behavioral design in their own modules / files to be used in the overall component design as...

Homework Statement Design a multiplexer circuit given the data such that: When ##C = 0##, the output ##X = A##. When ##C = 1##, the output ##X = B##. The truth table is displayed below: Homework EquationsThe Attempt at a Solution I wanted to make sure I understood this and I wasn't...

Homework Statement Design a 4 input priority encoder with a 4 to 16 decoder and a 8 to 1 multiplexer. Homework Equations Priority encoder is where when the highest priority bit is equal to a logical "1", then the rest of the lower priority input are ignored.The Attempt at a Solution For the...

If I want make 8 bit processor I think I need following think 1) ALU 2)control unit 1)ALU responsible for Arithmetic and logic Unit 2)control unit include with multiplexer and decoder circu main component for processor ALU 8 bit decoder multiplexer Q1 I have option for decoder decoder...

Consider f = w1w2! + w1w3 + w1!w2 +w1!w3! Use the truth table to derive a circuit for f that uses a 2-to-1 multiplexer I have the truth table, that part is easy. The problem I'm having is what exactly are they EVALUATING to get the f? Like I said I have the truth table of 3 input, but I don't...

Homework Statement Let f(x3; x2; x1; x0) = (y1; y0) such that y1 = 1 if the number of 1's in x3x2x1x0 is even, 0 otherwise, and, output y0 = 1 if the number of 1's in x3x2x1x0 is odd, 0 otherwise. 1. Implement f with four 2-to-4 decoders. 2. Implement f with a 4-to-1 multiplexer with selection...

Hello PF! I've been quite busy on my faculty, doing my academic final work. Anyway I need somebodies expertise which involves analog multiplexers. I am using MPC506 Datasheet http://www.ti.com/lit/gpn/mpc506 I tested it and gives nice result at 5 MHz sine wave, which is more than good for...

Can anyone help me with this question? I got the equation of the 2to 1 MUX. I got F = A'B' + AC. But the problem is I am not sure how to convert this into 4:1 MUX. Any help will be appreciated. Thanks

How do you implement different gates by using a two-input multiplexer? What are the inputs supposed to be? How do you implement an AND gate, for example? An OR?

Hi, I have a question regarding digital multiplexers. In communication systems, when we use mux, we can combine a lot of low bandwidth channels and transmit as a high bandwidth channel and then use a demux at the receiving end to split it back to the low bandwidth channels. I saw the...

Hi, new to the forums here. I'm looking for some help with multiplexers. I've created a 128-to-1 multiplexer with 8-to-1 multiplexers and one 2-to-1. Basically I have 16 8 to 1 in the first batch, 2 8 to 1 in the second and then a 2 to 1 to combine the last two. I'm assuming that's correct...

Homework Statement Hi, How to build a AND gate using a 2X1(2 inputs, 1 select,1 output) multiplexer? The same for a NOT gate? I am stuck on it! thank you Homework Equations The Attempt at a Solution Sorry I tried but I am confuse about what are consired as input if we decide...

Is it possible? Feasible?

Homework Statement LOGIC DESIGN USING MSI COMPONENTS A small corporation has 10 shares of stock, and each share entitles its owner to one vote at a stockholder’s meeting. The 10 shares of stock are owned by four people as follows: Mr.W; 1 share, Mr. X; 2 shares, Mr. Y; 3 shares, Mrs...

I cannot seem to understand how in the attached diagram, they went from the 4-1 multiplexer to the 2-1 multiplexer. The main part is the modified truth table. I can't understand what is going on for the life of me! If someone could please explain this, it would be much apprecieated. Thanks!

I have this ABEL file but can't figure out where 0, 1, 2, 3 come from in "when-then" statements... "The following ABEL code demonstrates how to implement a combinatorial multiplexer. " 4 to 1 multiplexer design SEL0..SEL1 pin; A,B,C,D pin; MUX_OUT pin istype 'com'; SEL = [SEL1,SEL0]...

I need to make a 2-1 mux using only NANDS and inverters. I thought it would look like a simple nand gate with another inverter attached at the end (basically a AND gate). However, that didnt work. I need it so when the selection input is a zero it selects whatever X0 is and when the selection...

Is there a systematic ways of expressing a boolean equation such as "ab+a'c" using multiplexer? Eyeballing and trial and error do not seem to work . What about decoder? Will k-map help? I have to design a 4 to 16 decoder using 2 to 4 decoder with some gates. I also have to design a full...