True or false:
a two input nor gate is designed to have the same worst case rise and fall times. The best case fall time is smaller than the best case rise time in this gate.
The Attempt at a Solution
The second part i get, the best case fall time is <best case rise time because for the fall time there are two paths for the current to to through in the parallel nmos tranisstors. But the rise time it still has to go through two series transistors?
thats my guess. but i don't get why the first part is true.