2NOR gate rise and fall time question

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Discussion Overview

The discussion revolves around the rise and fall times of a two-input NOR gate, exploring whether the gate is designed to have the same worst-case rise and fall times and the relationship between best-case fall and rise times. The context includes theoretical considerations and homework-related inquiries.

Discussion Character

  • Homework-related
  • Technical explanation
  • Conceptual clarification
  • Debate/contested

Main Points Raised

  • Some participants suggest that the best-case fall time is smaller than the best-case rise time due to the parallel configuration of NMOS transistors during fall time, while the rise time involves series transistors.
  • There is a request for the equivalent circuit used in the analysis, indicating that different configurations may yield different results.
  • Participants discuss factors affecting the output slew rate, including gate capacitance and output capacitance, and how these relate to rise and fall times.
  • One participant mentions that the course does not currently cover slew rate, focusing instead on rise and fall times approximated by the formula t(rise or fall) = 1.2 Req.C.
  • There is a discussion about how capacitance varies with process parameters and temperature, particularly in relation to transistor dimensions (W/L ratios) and mobility.
  • A participant questions the meaning of "corner" in the context of process variations, leading to a reference to process corners in integrated circuit design.
  • Another participant highlights the importance of understanding how output slew rate changes for NMOS versus PMOS transistors over temperature and process variations.
  • There is a correction regarding a previous statement about mobility and delay, emphasizing that as mobility decreases, delay increases.

Areas of Agreement / Disagreement

Participants express uncertainty regarding the first part of the homework question about worst-case rise and fall times, indicating a lack of consensus. Multiple competing views and interpretations of the circuit behavior are present.

Contextual Notes

Limitations include the absence of specific equations provided in the course that characterize rise and fall times, as well as assumptions about minimum transistor sizes not being explicitly stated. The discussion also reflects varying levels of familiarity with concepts like slew rate and process corners.

Who May Find This Useful

This discussion may be useful for students studying digital circuit design, particularly those interested in the timing characteristics of logic gates and the effects of process variations on circuit performance.

tdotengineer
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Homework Statement


True or false:
a two input nor gate is designed to have the same worst case rise and fall times. The best case fall time is smaller than the best case rise time in this gate.


Homework Equations


-

The Attempt at a Solution


The second part i get, the best case fall time is <best case rise time because for the fall time there are two paths for the current to to through in the parallel nmos tranisstors. But the rise time it still has to go through two series transistors?

thats my guess. but i don't get why the first part is true.
any help?
 
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tdotengineer said:

Homework Statement


True or false:
a two input nor gate is designed to have the same worst case rise and fall times. The best case fall time is smaller than the best case rise time in this gate.


Homework Equations


-

The Attempt at a Solution


The second part i get, the best case fall time is <best case rise time because for the fall time there are two paths for the current to to through in the parallel nmos tranisstors. But the rise time it still has to go through two series transistors?

thats my guess. but i don't get why the first part is true.
any help?

Can you post the equivalent circuit you are using for this? You can build NOR circuits lots of different ways...
 
berkeman said:
Can you post the equivalent circuit you are using for this? You can build NOR circuits lots of different ways...

oh sorry, this should do: nevermind the vdd value. Also please assume minimum transistor sizes (not stated in the question.. maybe I am wrong about assuming that)

img101.gif
 

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tdotengineer said:
oh sorry, this should do: nevermind the vdd value. Also please assume minimum transistor sizes (not stated in the question.. maybe I am wrong about assuming that)

img101.gif

Ah, that helps.

What-all determines the output slew rate of the gate?
 
berkeman said:
Ah, that helps.

What-all determines the output slew rate of the gate?

hmm, as for this course we don't deal with slew rate (not for now atleast), mostly
rise and fall times basically t(rise or fall)=1.2 Req.C aproximations

but looking up slew rate (wasnt sure what it exactly is)
e26070ff571c3008e6c0febf5fdf70c4.png
looks like it deals with saturation current and capacitance and gain (which I am not dealing with in this course as of now)

so some how relating the knowledge i just got from slew rate and what i know from my course I am finding the common thing to be the output capacitance

also the resistance of the network effects the delay times as well.
 
tdotengineer said:
hmm, as for this course we don't deal with slew rate (not for now atleast), mostly
rise and fall times basically t(rise or fall)=1.2 Req.C aproximations

but looking up slew rate (wasnt sure what it exactly is)
e26070ff571c3008e6c0febf5fdf70c4.png
looks like it deals with saturation current and capacitance and gain (which I am not dealing with in this course as of now)

so some how relating the knowledge i just got from slew rate and what i know from my course I am finding the common thing to be the output capacitance

also the resistance of the network effects the delay times as well.

I meant for slew rate to be one measure of the rise and fall times. Sorry if the term was confusing.

So yes, gate capacitance and output capacitance both will slow down the slew rate (lengthen the rise and fall times). What-all affects the gain? And how do both of those vary over process and temperature? What would you be doing to match the "worst case" slowest corner for the NMOS and PMOS devices? If you were in another corner of the process and temperature, which device changes more and why?
 
berkeman said:
I meant for slew rate to be one measure of the rise and fall times. Sorry if the term was confusing.

So yes, gate capacitance and output capacitance both will slow down the slew rate (lengthen the rise and fall times). What-all affects the gain? And how do both of those vary over process and temperature? What would you be doing to match the "worst case" slowest corner for the NMOS and PMOS devices? If you were in another corner of the process and temperature, which device changes more and why?

hmm I am not sure about gain. I know the capacitance varies over process because its related to the W/L's of the transistors also the oxide capacitance.

as for temperature i know its related to the mobility, meaning as temperature goes up mobility goes down and as mobility goes down the delay through a gate goes down as well, and from previous knowledge to match worse cases i would probably just adjust the W/L's of the transistors.

what do you mean by corner?
 
tdotengineer said:
hmm I am not sure about gain. I know the capacitance varies over process because its related to the W/L's of the transistors also the oxide capacitance.

as for temperature i know its related to the mobility, meaning as temperature goes up mobility goes down and as mobility goes down the delay through a gate goes down as well, and from previous knowledge to match worse cases i would probably just adjust the W/L's of the transistors.

what do you mean by corner?

See the Process Corners link off of this wikipedia IC design article:

http://en.wikipedia.org/wiki/Integrated_circuit_design

The reason I ask is because it sounds like this problem is asking for how the output slew rate changes for NMOS versus PMOS transistors (I would guess over temperature and process). Like, if one or the other had a larger variation of gain with temperature, that would help you answer the question, right?

BTW, I believe this is a small typo in the quoted text above:

as mobility goes down the delay through a gate goes down as well
 
tdotengineer said:

Homework Statement


True or false:
a two input nor gate is designed to have the same worst case rise and fall times. The best case fall time is smaller than the best case rise time in this gate.

This is not so easy to answer specifically to your course question without knowing some background.

What equations have you been given that characterized rise and fall times involving circuit parameters--and perhaps output loading.

Given these, then look for any change such that trise(P1)/tfall(P1) ≠ trise(P2)/tfall(P2), where the parameters, P could be anything such as gate-source capacitance that varies in process.
 
Last edited:
  • #10
berkeman said:
See the Process Corners link off of this wikipedia IC design article:

http://en.wikipedia.org/wiki/Integrated_circuit_design

The reason I ask is because it sounds like this problem is asking for how the output slew rate changes for NMOS versus PMOS transistors (I would guess over temperature and process). Like, if one or the other had a larger variation of gain with temperature, that would help you answer the question, right?

BTW, I believe this is a small typo in the quoted text above:
yes i believe so. I will have to think about it a little since my term test is today , but yes there was a typo, as mobility goes down the delay goes up!

Phrak said:
This is not so easy to answer specifically to your course question without knowing some background.

What equations have you been given that characterized rise and fall times involving circuit parameters--and perhaps output loading.

Given these, then look for any change such that trise(P1)/tfall(P1) ≠ trise(P2)/tfall(P2), where the parameters, P could be anything such as gate-source capacitance that varies in process.
yes i apologize, i was probably not clear enough. I'll that in mind for the future. Off to school now!
 

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