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About microprocessor 8085: state signals?

  1. Jun 16, 2013 #1
    Hello everyone! Could anyone explain to me the following: The 8085AH has 3 state signals: S0, S1 and IO/M*. S0 and S1 provide different type of machine cycles depending on their status.

    For example if the machine cycle is OpCode Fetch, we will get: S1=S0=1 and IO/M*=0. I don't get it though, what do the S1 and S0 signals actually do? I believe the processor decides their status with the help of the instruction decoder, and then what happens? They don't seem to connect to anything!

    Thank you for your time.

    Attached Files:

  2. jcsd
  3. Jun 18, 2013 #2


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    Code (Text):

    s0 s1
     0  0  halt
     0  1  read
     1  0  write
     1  1  fetch
    Link to pdf file:

    http://staff.neu.edu.tr/~kuyar/301/ch3.pdf [Broken]
    Last edited by a moderator: May 6, 2017
  4. Jun 18, 2013 #3
    rcgldr, thanks four your answer! However I still can't think of any way that these signals are useful. The processor decides first if it's halt, read, write or fetch (by decoding the instruction) and THEN updates the states of S0 and S1. Am I right?
  5. Jun 18, 2013 #4


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    S0 and S1 don't have to be used, since there are already other signals for read and write. Fetch will occur when reading instructions. If a program was coded carefully, fetch could be used to address some type of rom instead of main memory, effectively extending the address space. S0 and S1 are updated before a memory operation takes place.
  6. Jun 18, 2013 #5
    You could use S0 and S1 and some of the other status lines to create a "blinking light" front panel that would show what the processor is doing. It might be feasible to single step the processor one button press at a time and this would let you watch the status signals, address lines, data lines, etc.

    You could use S0 and S1 to build a hardware debugger that would allow you to stop the processor and grab control with a particular combination was observed.
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