Am I Analyzing This Op-Amp Circuit Correctly?

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cepheid
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Hey everyone. I'm wondering if I'm analyzing the attached op-amp circuit correctly. This is not homework, but rather, actual work. In the circuit diagram, VDAC is the output voltage of a DAC chip. VDAC and Vref are both measured relative to analog ground (AGND), as are the + and - power supply voltages for the op-amp (not shown). Here is what I came up with:

My understanding is that since an op-amp is a differential amplifier with a very large open loop gain, using it in this negative feedback configuration will cause differences between the inverting and non-inverting inputs to disappear (be "corrected") very quickly. Therfore, we can safely say that:

V+ = V-

There is a "virtual short" between them. Since the + input is connected to the DAC output voltage, it follows that:

V- = VDAC

Now, assuming infinite input impedance (as in the ideal case), no current flows into the inverting input. Therefore, I have assumed that a current I flows from the op-amp output, through the feedback resistor, and then through resistor RINV into the Vref node. (All of these nodes are actually pins of ICs, and I'm assuming that they can sink some current). Since the resistors are in series, I obtain expressions for the current I very simply from Ohm's law:

[tex] I = \frac{V_{\textrm{out}} - V_{\textrm{DAC}}}{R_{\textrm{FB}}} = \frac{V_{\textrm{DAC}} - V_{\textrm{ref}}}{R_{\textrm{INV}}} [/tex]​

Next, I solved for Vout:

[tex] \frac{V_{\textrm{out}}}{R_{\textrm{FB}}} = \frac{V_{\textrm{DAC}}}{R_{\textrm{FB}}} + \frac{V_{\textrm{DAC}}}{R_{\textrm{INV}}} - \frac{V_{\textrm{ref}}}{R_{\textrm{INV}}} [/tex]

[tex] V_{\textrm{out}} = V_{\textrm{DAC}}\left(1 + \frac{R_{\textrm{FB}}}{R_{\textrm{INV}}}\right)- V_{\textrm{ref}}\frac{R_{\textrm{FB}}}{R_{\textrm{INV}}} [/tex]​

Now, here's the part that's puzzling me. The purpose of connecting the DAC chip's output to an external op-amp in this configuration is to create a bipolar output from a unipolar one. Now, on the one hand, the DAC chip's datasheet claims that RFB/RINV = 1 (these resistors are internal to the DAC chip). On the other hand, it claims that this exact external op-amp configuration results in "unity gain and and offset of -Vref/2." That suggests that it converts the DAC output range from (0 to +Vref) to (-Vref/2 to +Vref/2). HOWEVER, if I plug RFB/RINV = 1 into the equation I derived for Vout, I get a gain of 2 and an offset of -Vref. It seems like I'm missing a factor of 1/2 somewhere. What did I do wrong?
 

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  • #2
phyzguy
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I think that you've analyzed it correctly, and if Rinv = Rfb then it will convert a Vdac input of 0->Vref to an output of -Vref to +Vref. Maybe this is what they mean by "unity gain", although I would agree with you that this is a gain of 2. Can you hook it up and try it out?
 
  • #3
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Can you post the DAC chip part number? I design a lot of DAC circuit, I never encounter one like your description. Usually I use current DAC so I all I did was connect half full scale current to switch to bi-polar output.

Your calculation make sense, just the circuit is kind of odd looking. From the given [itex]R_{fb}=R_{inv}[/itex], I assuming at full scale, [itex]V_{DAC}= V_{REF}[/itex] so output of the amp is [itex]V_{REF}[/itex]. The amplifier has +ve gain of 2. So when the [itex]V_{DAC}= 0V[/itex], then the output of the amp is [itex]-V_{REF}[/itex]. So you get a non inverting from uni-polar to bi-polar output of +/- [itex]V_{REF}[/itex]. But this is very uncommon way of doing it!!!

If that is what you expect, it works!!!
 
  • #5
cepheid
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I think that you've analyzed it correctly, and if Rinv = Rfb then it will convert a Vdac input of 0->Vref to an output of -Vref to +Vref. Maybe this is what they mean by "unity gain", although I would agree with you that this is a gain of 2. Can you hook it up and try it out?
Hey phyzguy -- actually testing the output is a good suggestion, and I'm just at the point where I'm able to do so. (I've been plagued with problems trying to get all of this working up to now!). I have the ability to send five different input values to each of five different "DAC boards" (described briefly below). So I'll pick five values that span the range between 0x0000 and 0xffff and get back to you tomorrow. As it happens, Vref = +2.5 V, so if you and I are correct, the output values should range between -2.5 V and +2.5 V. If the datasheet is correct (and somehow it is literally unity gain), then I guess the values will range between -1.25 V and + 1.25 V.


Can you post the DAC chip part number? I design a lot of DAC circuit, I never encounter one like your description. Usually I use current DAC so I all I did was connect half full scale current to switch to bi-polar output.

Your calculation make sense, just the circuit is kind of odd looking. From the given [itex]R_{fb}=R_{inv}[/itex], I assuming at full scale, [itex]V_{DAC}= V_{REF}[/itex] so output of the amp is [itex]V_{REF}[/itex]. The amplifier has +ve gain of 2. So when the [itex]V_{DAC}= 0V[/itex], then the output of the amp is [itex]-V_{REF}[/itex]. So you get a non inverting from uni-polar to bi-polar output of +/- [itex]V_{REF}[/itex]. But this is very uncommon way of doing it!!!

If that is what you expect, it works!!!
The DAC chip is a Maxim 542 16-bit serial DAC. If you check out the datasheet for it, I believe you will find that the op-amp circuit I posted, however unusual it may be, is the recommended circuit for a bipolar output. It is encouraging that you agree with mine and phyzguy's assessment that the gain is 2 and the offset is -Vref, so that the output should range between -Vref and +Vref. (We shall see tomorrow!)

More details: I believe the DAC interface is "SPI bus compatible" meaning that it consists of three different signals. There is the serial data input (known as MOSI for "master output, slave input"). Then there is a CLK signal. Finally, there is a SEL (chip select) signal that is active low. If SEL is low, then on every falling clock edge, the chip reads in the value of the bit on MOSI. Once 16 bits have been read, this input is "latched in." My "DAC boards" are custom PCBs that contain, in addition to the DAC chip itself, a precision voltage reference (Maxim 6225, the source of Vref = +2.5 V), and two external op-amps. The first external op-amp circuit is the one in my OP. The second one, as far as I can tell, is just a unity-gain inverting amplifier that takes Vout from the first op-amp and produces -Vout. Therefore, if I take the output voltage of my DAC board as being between +Vout and -Vout, then in principle the board should actually be able to produce outputs ranging between -2Vref and + 2Vref. I did not design these boards or even build them. I am merely trying to understand them so that I can get them to work.



See derivation of a fully differential op-amp circuit at

http://www.electronics-tutorials.ws/opamp/opamp_5.html

Bob S
Hey Bob S: I read the information at that link, and I notice that that circuit is very similar to mine, except that in my circuit, there is no resistor in the place occupied by R4. It is very promising that, in the second last equation (the one before the one that is in a yellow box), if you let [itex] R_4 \longrightarrow \infty [/itex], the second factor in parentheses in the first term on the right hand side goes to unity, and what is left is exactly the same as what I derived (with R3 = RFB and R1 = RINV). So that's a great confirmation.

Thanks a lot for all the help guys! I really appreciate it.
 
  • #6
cepheid
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Okay, based on the tests I've done, I'm pretty sure that we're right and the outputs range from -Vref to +Vref. Now I have a new problem, which is that the DAC output is not always consistent with its input. I'm working on that...
 
  • #7
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Okay, based on the tests I've done, I'm pretty sure that we're right and the outputs range from -Vref to +Vref. Now I have a new problem, which is that the DAC output is not always consistent with its input. I'm working on that...
What do you mean? Is it the analog output does not match the digital SPI input value you put in? If so, then the best way is to use a storage scope, trigger on the /CS ( chip select) or CLK and read every "bit" on the SPI stream to make sure you sent the right value.

About the original post, if it is a circuit given by the application data sheet, then you should be able to trust it. It just look a little different from my experience, nothing more. Besides my experience is five years old already!!!
 
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  • #8
berkeman
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If you do suspect an SPI interface problem, you can use a serial bus analyzer like the Beagle from TotalPhase ($300):

http://www.totalphase.com/products/beagle_ism/

Debugging with a digital 'scope can be done, but the Beagle makes it a lot easier and faster. I've done it both ways, and try to use the Beagle when practical. It's easier to justify the $300 if you work with SPI a lot in your projects, though.
 
  • #9
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Using the scope is easier than people think. Yes, if you do a lot of SPI, then it's worth the $300. If it is a onesy thing, you can do the scope thing in no time.
 
  • #10
cepheid
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What do you mean? Is it the analog output does not match the digital SPI input value you put in?
Yes, exactly. For some values, it seems to work fine. At one point I was inputting 0xabcd, for which I'd predict an output of 0.855 V (bipolar), and I got something pretty close, but typically lower by a few 10s of mV. Then, taking physzguy's advice, I set my five DAC values to span the full range of possible values: (0x0000, 0x4000, 0xc000, 0xffff). None of the first four of these worked -- they all resulted in an output of 0.000 V (raw -- i.e. -2.5 V from the bipolar output). Only the input of 0xffff worked, producing an output of +2.498 V.

It's interesting to note that the 16-bit codes that didn't work each have only one (or two) bits that are set ("high"). So, it almost seems as though the DAC chip is not recognizing some 1's as being 1's. If there are too few of them in the word, the input will be interpreted as 0. That's my best working theory, although I have no idea why it is happening or how to fix it. EDIT: It's not a threshold problem. The datasheet says that the minimum VIH (input high voltage) is 2.4 V. The value of the signal on my data line is very close to +5.0 V when it is a "logic high."

If so, then the best way is to use a storage scope, trigger on the /CS ( chip select) or CLK and read every "bit" on the SPI stream to make sure you sent the right value.
I've been doing just that for quite a while, my friend. We have a pretty decent digital oscilloscope in my lab, and I've checked the SPI signals all the way down the line, including right at the pins of the DAC IC. CLK, SEL, and MOSI all look fine, and I've verified bit by bit that the data being written are correct. I know what the data inputs are supposed to be, because I programmed them into the DSP that drives all of this.

The scope trace for the DAC chip's output pin seems to vary from one DAC board to another. In one case, the DAC output was 0.000 V measured on a Fluke DMM, and on the scope, the output appeared completely flat. In another case, the measured output was more like 0.3-0.4 V (still too low for the input code), and the scope trace appeared mostly flat with intermittent square pulses of varying duration. It was almost as if the DAC chip was working sometimes, causing the output to pulse to the expected value very briefly, but not working most of the time. With a third DAC board, I also saw this behaviour, except that the pulses were even narrower and less frequent.

I've attached a PDF of the schematic for one of my DAC boards in case any of you have any insights. The actual chips soldered on differ from the ones indicated by the schematic in some cases. The DAC chip is actually an AD5542 from Analog Devices, but as far as I can tell, it is identical to its Maxim counterpart. The op-amps being used are actually OP297s. From all the probing I've done, it seems like the RS485 receivers, the precision voltage reference, and the op-amps are all working fine. Everything is good on the input side of the DAC chip. I can't understand what the problem is.

EDIT: Berkeman -- I'm not really authorized to buy that analyzer at the moment, but thanks for the link. For the time being, I'll have to make do with the scope.
 

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  • #11
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I worked for LeCroy for a few years as a design engineer of three transient recorders. They design all sorts of trancient recorders, digital scopes etc. We used all sort of techniques to design high speed ADCs using subrange configurations that involved DACs. You'll be surprised how many of them fail when you run them in the rated speed. You'll be surprised how often they have problems. I went into the manufacturer to prove to them that they had problem with their products a few times. This include Burt Brown.

Write a program, writing to the DAC as fast as the spec called for with an incrementing binary data. Observe the output of the DAC to look at the ramp for missing codes. You can see it from a bit that is out of place. You can speed it up by using only 12 bit counter instead of 16 to check the slew rate. Make sure you run both increment and decrement to look and both polarities of the ramp. This is part of testing I learnt from Walter Lecroy the founder of LeCroy when I was luckly enough to work directly under him in the early 80s.

Make sure also you check the data setup and hold time of the SPI input to meet the requirements printed on the data sheet of the DAC. You don't know how many times I fixed other people's nightmare due to the setup and hold time requirement. Digital stuff is very very easy. Most of the problems are related to setup and hold time and people using the carry out of the counter as clock for other logics in AHDL or VHDL!!! You be careful of that, you seldom run into problem. I personally never seen a digital problem that I cannot resolve yet. They are not analog or RF, they are just that easy......And I design micro controllers, FPGAs, giga hertz ECL logics and anything in between throughout the years.....Well just make sure the software is doing the job!!!!!
 
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