Body effect for NMOS transistor

So in summary, the higher the gate voltage, the more electrons are attracted to the gate and the inversion layer is created using electrons from the source terminal.f
  • #1
I would like to know why the threshold voltage increases for an NMOS transistor when the voltage difference between the source and the body terminals is greater than 0.

If, for example, the body terminal is connected to -1V and the source to 0V, holes from the p-substrate are attracted to this terminal, leaving behind negative ions (atoms whose "holes" were occupied by electrons).

Why does this mean that a higher gate voltage is required to form the channel (consisting of electrons)?

Thank you.
  • #2
Well those negative ions that are left behind have to be compensated by something, right? That compensating voltage is in series with the MOSFET gate so it has the same effect as increasing the threshold voltage. This is the body effect.
  • #3
But if the holes are attracted by the bulk terminal, leaving under the gate negative ions, why wouldn't just a small positive voltage on the gate attract more electrons to form the channel? Is it because the negative ions somehow "repel" the electrons that would normally start forming the channel?
  • #4
You're close! A positive voltage does attract electrons, but the first 'bit' of positive voltage is needed to cancel the field created by the space charges uncovered by body effect. So the first part of the voltage you apply is taken up by these ions and so doesn't contribute to the turn on of the device.
  • #5
So I was right, the negative ions repel the electrons that would normally form the channel. I have another question, somehow related. Is is correct that the channel is mainly formed of electrons that come from the source terminal? Thank you very much for your time!
  • #6
I think it is a bit more subtle than that. My understand as a circuit designer (and not a physicist) is that the channel is formed by electrons from the bulk that are attracted to the gate potential. This is called inversion. Any current through the device comes from the source terminal as you said (neglecting second-order effects).
  • #7
I was told (and I think the person who told me quoted from a book, so it should be true) that the inversion layer is created using electrons from the source terminal because free electrons in the bulk appear only because of the thermal agitation (so their number is limited) and it would take too much time to create the channel this way. The reason why I asked about this is because if electrons come from the source terminal, the electric field caused by the negative ions wouldn't have such a big effect on them compared to the situation where the electrons came from the bulk.
  • #8
You could be right. Like I said I'm a chip designer, not a physicist. However, it does surprise me that the inversion layer electrons would come from the source. Could be, though, since you need a bias current to remain in saturation.
  • #9
Hey I partially take that back. There is an inversion layer when the device is in triode when (in a digital context) no current flows. That makes me skeptical that the electrons would come from the source. Hmmm... I've been designing chips for 15 years and this has never come up... interesting.
  • #10
I found my post ( and the first answer contains this quote from a book (I hope I am allowed to add links to other sites):

"In the above discussion you may have wondered, “Where do the electrons come from to form the inversion layer?” In the body of the MOS-C structure, electrons are minority carriers and few and far between. So when inversion occurs, where do we find all the electrons necessary to invert the surface? Well, there was a subtle assumption that if we apply a change in gate voltage, we wait long enough for thermal generation to create a sufficient number of electrons to form the surface layer. We may have to wait a very long time! In other words, if we apply a fast enough signal to the gate, there isn’t enough time for the minority carriers to be generated and thus the capacitance remains at the low value given by depletion.

While the depletion region can respond very quickly to our gate voltage since it is formed by majority carriers, the minority carrier generation is slow. There is a simple way to solve this problem, as shown in Fig. 2.25, where a n+ grounded contact is placed adjacent to the gate. Normally electrons are prevented from entering the body, like any good pn-junction. But as we raise the surface potential, electrons can easily diffuse into the surface of the structure. Since the energy distribution of electrons in thermal equilibrium is exponential, changing the potential barrier linearly results in an exponential increase in the number of electrons that can cross the n+-surface junction and likewise an exponential increase in surface conductors."
  • #11
Oh ok it's coming back to me. Haven't thought about this stuff since school. The source of electrons can't be the source because the same effect happens in an MOS capacitor which has no source or drain. Here is a quote from a lecture about MOS caps (they are talking about a PMOS cap here)

Where do the holes that form the inversion layer come from?
In a MOS capacitor in depletion or inversion, the holes and electrons are generated in the depleted silicon surface
region. The holes are attracted to the Si/SiO2 interface while the electrons are “pushed” into the
bstrate. However the holes could also come from a p-doped region that is in close proximity to
e MOS capacitor such as the source/drain region of a p-MOSFET.

Here's the whole lecture:
  • #12
"However the holes could also come from a p-doped region that is in close proximity to
e MOS capacitor such as the source/drain region of a p-MOSFET."

Maybe this could happen inside a mosfet as well. I thought about this only because if the electrons do come from the source, then the electric field caused by the negative ions would not affect them as much as if they were coming from the bulk, correct?

Thank you very much for you help and time!

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