Dismiss Notice
Join Physics Forums Today!
The friendliest, high quality science and math community on the planet! Everyone who loves science is here!

Saturation and pinch off in enhancement mosfets

  1. May 19, 2016 #1
    Hello! Is there a difference between satutation and pinch off in nmos transistors? Because my research in the internet for Mosfet pinch off leave me think that there is no difference between the two. Which confuses me, because pinch off means that there is no current at all, and saturation means that there is, but it has reached its maximum value. Also i dont think i fully understand the process of pinch off in enhancement mosfets. My understanding is that once the inversion layer is formed and a voltage is applied between the drain and the source, current start flowing. If we increase Vds too much, the strong electric field of the drain began to sink electrons from the chanel and it shrinks. If we increase it even more, the drain sinks so much electrons that basicaly a depletion layer is formed. Is that correct? Also how to determine at what value of Vds pinch off will occure?
     
    Last edited by a moderator: May 23, 2016
  2. jcsd
  3. May 24, 2016 #2
    Thanks for the post! This is an automated courtesy bump. Sorry you aren't generating responses at the moment. Do you have any further information, come to any new conclusions or is it possible to reword the post?
     
  4. May 24, 2016 #3

    analogdesign

    User Avatar
    Science Advisor

    Hi Genji,

    Pinch-off is the edge of saturation (the point where the triode region goes to the saturation region). it is not the current being pinched-off but rather the inversion region underneath the gate (it is pinched off right at the drain). As you increase VDS while in saturation region, the channel remains pinched off but the depletion region between the inversion layer and the drain gets larger.

    Remember that in triode region the MOSFET works as a linear resistor, and when you increase VDS the inversion layer under the gate gets thinner and thinner near the drain. The current goes up also when you increase VDS because of Ohm's Law. When the inversion layer right below the gate gets so thin it disappears this is called the edge of saturation.

    The value of Vds that causes pinch off is just VGS-VT since this is just the definition of saturation (VGS > VT & VGD > 0).
     
  5. May 26, 2016 #4
    Thank you!
     
  6. Jan 13, 2017 #5
    It is said that the current saturates at a certain Vds, but actually it doesn't. There is still a very little increase in the source to drain current, may be very little , almost negligible but still there are some increment. Why is that? I got it in my lab project for MOSFET while observing the output characteristics of MOSFET.
     
  7. Jan 13, 2017 #6

    analogdesign

    User Avatar
    Science Advisor

    In an ideal MOSFET, the current does saturate. However, an ideal MOSFET as infinite output resistance and real MOSFETs have finite output resistance, as you have observed in your lab project. I gave the reason in an earlier comment:

    This is called "channel length modulation" and you can look it up. The core reason is that when you increase VDS the depletion region gets larger and it makes the effective length of the MOSFET shorter. Since the drain current in saturation is proportional to W/L this means the current increase.
     
Know someone interested in this topic? Share this thread via Reddit, Google+, Twitter, or Facebook

Have something to add?
Draft saved Draft deleted



Similar Discussions: Saturation and pinch off in enhancement mosfets
Loading...