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Boolean Algebra VS Karnaugh map

  1. Jan 2, 2012 #1


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    We were taught both methods to minimize gates. I frankly just wanna pick one method all the time and become an expert in it, rather then try them both. So, according to your experience, which method do I better pick?
  2. jcsd
  3. Jan 2, 2012 #2
    There is significantly less call for these types of analyses these days. Many functions, formerly created in hardware are now realized in software and there is software available to perform the analysis of complicated systems.

    I'm going to stick my neck out here and recommend sticking with truth tables, Boole and De Morgan for occasional use.

    You really need to be using K maps or other advanced techniques all the time or you may miss something vital. They can however provide short cuts.

    go well and enjoy the new year
  4. Jan 2, 2012 #3
    For simplifying complex expressions the Karnaugh maps can reduce the factoring time by a factor of ten. However, you have to draw the maps which takes time. If you get really good at the algebra it's effective enough but you can miss a reduction that the map would let you spot trivially.

    I used to use the algebra until I was shown the maps. I only use the maps unless the expression is fairly simple.

    Truh is you need to be comfortable with both if you're going to be an EE. Bigger truth is you won't use either in professional practice since the automated tools do it for you now as was mentioned above.
  5. Jan 2, 2012 #4
    Honestly, I don't use either one that often when I design digital circuits. I pretty much agree with Studiot. I don't even remember what exactly Karnaugh map is anymore. Now a days, everything is done in processors and FPGAs, it is like writing programs in hardware language.
  6. Jan 2, 2012 #5
    I would say you need to be comfortable with both.
    You also need to bear in mind that a lot of the time there is no point simplifying logic. In an FPGA design, for example, it makes no difference to what actually gets put into the device if you simplify the logic or not. Sometimes simplification disguises function, which is usually not a good thing.
  7. Jan 2, 2012 #6
    I don't know about disguising function but you are right the logically most compact (=simplest) may not make best use of available chips, leaving many gates unused or demanding a particular type that requires a different chip.

    Further if you are constrained to a specific bus size 4,8,16 etc bits you have to put something on each bit, whether your simplified logic uses it or not.

    As always, good engineering design is a blend of balancing competing requirements.
  8. Jan 2, 2012 #7
    The most important thing to make a good digital design is not about minimum amount of logic gates or the simplest function. The me, the most effort is to make sure the timing is correct. Making sure the setup and hold time is met for any memory, latch or flip-flop etc. So many unstable designs are due to violation of timing. This is important in FPGA programming. Face it, writing those program is so easy, just like writing any of the software programming. The trick is to write in the timing so you guaranty by design you don't produce glitches, violation of timing.

    Another important thing is to make sure you don't have glitches in the logic when different inputs transition to a new state. For example if two input of an AND gate where one goes from 1 to 0 while and other goes from 0 to 1. In the ideal world, the output stays 0 before and after the transition. But in real life you can have a glitch where the second input transition to 1 before the first input transition to 0. If you use this to clock a latch, a memory etc, you might clock in garbage.

    I was pretty much force into learning how to program FPGAs because the supposed expert in FPGA screwed up. The system was intermittent for the longest time.

    Learn how to draw timing diagram and draw timing diagram on all the design, take into consideration of the minimum and maximum delay variation and make sure you get enough setup and hold time, minimum cycle time etc.

    With this care, I yet to have any intermittent designs yet. I used to test my processor boards, embedded board with FPGAs with heat gun, freeze spray, rubbing moist hand at the back of the board to give variations and proof it work perfect. A good design is to get the job done reliably, not the one with the fewest components. My design time is about 25% design and 75% checking timing requirement. It is boring, nothing exciting like designing circuit, but that's the price to pay to avoid trouble later.

    That was the reason my test for any EE applicant contain one timing diagram drawing......nothing complicated, just a D-FF as divided by two and qualified with a second D-FF. Given the initial condition and start clocking. You'll be surprise how many cannot do it.
    Last edited: Jan 2, 2012
  9. Jan 2, 2012 #8
    Lot's of good advice here, but remember Femme Physics is constrained by her course.
  10. Jan 2, 2012 #9
    I actually learn about timing diagram in my first digital class for AA degree in Heald College. Somehow, it just stuck with me and it served me very well.
  11. Jan 3, 2012 #10
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