D-Flip-Flop Circuit: Understanding the Enable and Clock Input Functions

• SnoopyElectron
In summary, the conversation revolves around a circuit designed for second year engineering (electrical). The confusion lies in the use of a switch and a capacitor connected to a LED, and how the LED stays lit up the entire time the switch is pressed. The goal is to enable the gate at the start of each clock pulse, rather than throughout the whole pulse, for synchronisation purposes. The LED is connected to both resistors and the capacitor, and the capacitor discharges when the switch is open. A schematic is recommended to avoid confusion and ensure proper understanding of the circuit.
SnoopyElectron

So I have been watching his videos trying to get ready for second year engineering (electrical). However, I am very confused as to what exactly is going on when he is pressing the enable/pulse switch during the run-through at 14:45. He has the enable connected to a capacitor, and he calculates the time constant of it to be 0.1 ms.

Now, my question is, why does the topmost LED that is connected to the enable & capacitor stay lit up the entire time that he is pressing the switch down? Doesn't the 0.1 ms time constant mean that current can only travel through that LED for 0.1 ms, and thus only light up for 0.1 ms ?

To be frank, I am not even sure why he is holding the switch down to correspond with the 'CLK' rate, if the goal is to make the 'EN' input the enabler, not the CLK rate.

I am not sure what I am misunderstanding, and any help would be appreciated.Thanks

SnoopyElectron said:
Now, my question is, why does the topmost LED that is connected to the enable & capacitor stay lit up the entire time that he is pressing the switch down? Doesn't the 0.1 ms time constant mean that current can only travel through that LED for 0.1 ms, and thus only light up for 0.1 ms ?
The LED is in the switch cct before the capacitor. The switch connects the LED to the +5V, so it stays on as long as the switch is pressed. The output from this cct goes through the capacitor to the enable input of the gate. The current from the {+5V, switch, LED, resistor, Gnd } combination flows through the capacitor to the new 1k resistor and the enable input, for only a brief moment. (Notice now, there are two resistors, not one.)
To be frank, I am not even sure why he is holding the switch down to correspond with the 'CLK' rate, if the goal is to make the 'EN' input the enabler, not the CLK rate.
The goal is to make the 'EN' input the enabler, but only at the instant when the Clk pulse rises.
Instead of enabling the gate throughout the whole of the clock pulse, which is what would happen if you just applied the clock signal to the 'Enable' input, he wants to enable the gate just for the start of each clock pulse. That way, the output will only ever change at the same time as the start of the clock pulse, rather than when the data input changes. The data input still decides what the output will be, but only at the start of each clock pulse. The rest of the time it is locked and steady, so that other circuits can read the output reliably.

The reason for having a clock signal is synchronisation, to ensure that all the logic circuits change at the same, predictable time.

SnoopyElectron
Let's call the top resistor RA and the middle one RB. I guess what i am confused about is how the top LED is connected to both RA and the capacitor, since RA and the capacitor are in different conducting "rows" (not sure the about the correct terminology). Its hard to see which rows the two arms of the LED are connected to.

One more question for you, how is the capacitor discharging in this process? Like what would be the resulting closed circuit when the switch is open, in which the capacitor can discharge? I would think that when the capacitor discharges, it would also send another mini pulse through the two input wires it is connected to, thus creating double the amount of intended pulses.

Sorry for the confusion, and thanks for all your help

I'm not able to watch the video while I'm at work. Can you upload a snapshot of the circuit?

SnoopyElectron

https://gyazo.com/4b7da1973d7f1c7d89b8788fb62a20b1
above is a screenshot of the circuit. after the capacitor and RB are added (note the values are not correct, just the reference designators). The circuit functionality is explained well by Merlin.
The reason for the two wires is the same signal needs to be sent to two different inputs.

To reiterate what merlin said, When the switch is open, Ra and Rb pull down the voltage on either side of c1, allowing the cap to discharge. When the switch is turned on, 5 volts gets put instantaneously across the capacitor and led. The led turns on with its current being set by RA. current only flows through caps when the voltage changes ( I = 1/(C) dv/dt ), which means that current olny flows through RB during the first second the switch is pressed.Also I just found a free program online called circuit lab that allows you to quickly and easily draw circuits. https://www.circuitlab.com/
seems like it would be very useful for this type of occasion

edit: ahhh you beat me to a circuit schematic

SnoopyElectron
okay thanks very much for your help. It was just hard for me to see from his breadboard setup how the LED is connected to both RA and the capacitor, but i guess i just have to accept that, since your schematic does indeed make sense lol.

donpacino
SnoopyElectron said:
okay thanks very much for your help. It was just hard for me to see from his breadboard setup how the LED is connected to both RA and the capacitor, but i guess i just have to accept that, since your schematic does indeed make sense lol.

Often breadboards, pcbs, etc can be confusing to look at the layout. A properly prepared engineer will always try to obtain or derive a schematic (or paritial schematic) before moving further. Even if it is a seemingly simply circuit, drawing out the schematic on paper can save a lot of confusion and hassle later on!

note: asking for help counts as trying to obtain a schematic!

Here's my circuit. Left is the original, right with capacitor. ( Ignore the 10Ω resistor, that's just my quirk!)

In the original, when the switch is closed, the middle wire goes up to 5V and stays there until the switch is released, when it falls back to zero.
The same happens in the new circuit. The capacitor starts uncharged, so the full 5V is applied across the 10k resistor, but as it charges up, more volyage is across the capacitor and less across the resistor. When the capacitor is fully charged, 5V across it, there is no voltage left across the 10k. So the output is an initial 5V spike falling quickly to zero.
When the switch is released and the left side of the capacitor falls towards zero, the 5V across the capacitor drives current back through the LED and the 330 and 10k resistors, causing a negative spike on the output.. This is normally bypassed by a diode across the 10k, so that it does not affect the output. But this inverse "mini pulse" is in the wrong direction to enable the latch, so the latch won't get enabled twice per clock pulse. (But, I'd remove it, because the negative pulse could damage the chip and also cause undefined behaviour. I think some families of gates like 4000 CMOS have built in protection diodes.)

donpacino and SnoopyElectron
Merlin3189 said:
Here's my circuit. Left is the original, right with capacitor. ( Ignore the 10Ω resistor, that's just my quirk!)
View attachment 208062
In the original, when the switch is closed, the middle wire goes up to 5V and stays there until the switch is released, when it falls back to zero.
The same happens in the new circuit. The capacitor starts uncharged, so the full 5V is applied across the 10k resistor, but as it charges up, more volyage is across the capacitor and less across the resistor. When the capacitor is fully charged, 5V across it, there is no voltage left across the 10k. So the output is an initial 5V spike falling quickly to zero.
When the switch is released and the left side of the capacitor falls towards zero, the 5V across the capacitor drives current back through the LED and the 330 and 10k resistors, causing a negative spike on the output.. This is normally bypassed by a diode across the 10k, so that it does not affect the output. But this inverse "mini pulse" is in the wrong direction to enable the latch, so the latch won't get enabled twice per clock pulse. (But, I'd remove it, because the negative pulse could damage the chip and also cause undefined behaviour. I think some families of gates like 4000 CMOS have built in protection diodes.)

By stating that the "'mini pulse' is in the wrong direction enable the latch," do you mean that the electrons will not choose to flow through the "AND" gates in order to reach ground, since they prefer the routes RA and RB provide. Also, after the electrons discharge through 330/RA, won't that cause the LED to light up for a brief moment?

Looking at Q1, the input circuit: When a high voltage (+5V) is applied to both inputs, the transistor is cut off, because both emitters are reverse biased.
When either input is low, Q1 is switched on because the emitter is forward biased.
If an input is below zero (negative) then Q1 will still be switched on because the emitter is forward biased. D1/2 are just added for protection, because a negative input could draw too much current.
The rest of the circuit (which varies) is just to convert the output of Q1 to the required high or low and to provide enough output current to drive more gates.

Diode D1 or D2 will be reverse-biased on a high input and have no voltage across it on a low input, and therefore not conduct any current. The purpose for having D1/2 in the circuit is to prevent transistor damage in the case of a negative voltage being impressed on the input (a voltage that is negative, rather than positive, with respect to ground).

Edit: Oh yes, the discharge of C will provide a momentary drive for the LED. You won't see it though. The LED is on via the switch and C discharging just keeps the current going for a fraction of a second after the switch is flipped. So it just merges into the normal LED on period: instead of switching off sharply, it fades gently (over a few microseconds, so you won't notice even that !)

Edit2: Just realized I didn't answer specifically, so added bit in blue.

Last edited:
SnoopyElectron
Merlin3189 said:
View attachment 208089
Looking at Q1, the input circuit: When a high voltage (+5V) is applied to both inputs, the transistor is cut off, because both emitters are reverse biased.
When either input is low, Q1 is switched on because the emitter is forward biased.
If an input is below zero (negative) then Q1 will still be switched on because the emitter is forward biased. D1/2 are just added for protection, because a negative input could draw too much current.
The rest of the circuit (which varies) is just to convert the output of Q1 to the required high or low and to provide enough output current to drive more gates.

Diode D1 or D2 will be reverse-biased on a high input and have no voltage across it on a low input, and therefore not conduct any current. The purpose for having D1/2 in the circuit is to prevent transistor damage in the case of a negative voltage being impressed on the input (a voltage that is negative, rather than positive, with respect to ground).

Edit: Oh yes, the discharge of C will provide a momentary drive for the LED. You won't see it though. The LED is on via the switch and C discharging just keeps the current going for a fraction of a second after the switch is flipped. So it just merges into the normal LED on period: instead of switching off sharply, it fades gently (over a few microseconds, so you won't notice even that !)

Edit2: Just realized I didn't answer specifically, so added bit in blue.
thank you so much

1. What is a D-Flip-Flop circuit?

A D-Flip-Flop circuit is a digital logic circuit that is used to store a single bit of information. It has two stable states, 0 and 1, which are known as the "reset" and "set" states, respectively.

2. What is the purpose of the Enable input in a D-Flip-Flop circuit?

The Enable input in a D-Flip-Flop circuit is used to control when the circuit will respond to changes in the data input. When the Enable input is high, the circuit will respond to changes in the data input, but when it is low, the circuit will hold its current state, ignoring any changes in the data input.

3. How does the Clock input function in a D-Flip-Flop circuit?

The Clock input in a D-Flip-Flop circuit is used to synchronize the circuit with an external clock signal. When the clock signal transitions from low to high, the circuit will read the data input and store it in its internal memory. This allows the circuit to operate at the same rate as the external clock signal.

4. What happens when both the Enable and Clock inputs are high in a D-Flip-Flop circuit?

When both the Enable and Clock inputs are high, the D-Flip-Flop circuit will respond to changes in the data input on each rising edge of the clock signal. This is known as the "edge-triggered" mode, and it allows for precise control over when the circuit will store data.

5. How is a D-Flip-Flop circuit different from other types of Flip-Flop circuits?

A D-Flip-Flop circuit is different from other types of Flip-Flop circuits because it only has one data input, whereas other types may have multiple inputs. Additionally, the D-Flip-Flop circuit is edge-triggered, while others may be level-triggered, meaning they respond to changes in the data input at any time, not just on the rising edge of the clock signal.

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