# Designing 8-bit Binary to BDC Converter

Designing 8-bit Binary to BCD Converter

I have to design and implement an 8-bit binary to BCD converter **using only ICs**

I have an algorithm that works just fine in converting an 8-bit binary to BCD that can be sent to three 7-segment displays. It is called the double dabble method. Please look at the Wiki article below if you don't know what this is because you will be lost with my method if you are not familiar.

http://en.wikipedia.org/wiki/Double_dabble" [Broken]

I have a series of 10 D FFs hooked up as a serial shift register. I have a parallel in, serial out shift register before the 10 D FFs so I can load the 8-bit number and then progressively shift it as needed by the double dabble method.

The first 4 FFs represent the 1's place, the next 4 represent the 10's place and the last 2 FFs are for the 100's place (only 2 because the hundreds place can only go as high 2).

I am thinking of setting up comparators to the 1's and 10's place FF outputs and tying one of each comparator's inputs to binary 0100 (4 in decimal) to see when the number in the 1's and 10's place is greater than 4. When that is the case, I want to use use that (A>B) output to add 3 (0011) to whatever number is in the place in question (1's or 10's). I can do this with a 4-bit adder.

Now is where I am getting lost. I want to some how use the output of the comparator to take the sum of the 4-bit adder and put that BACK INTO the place of the original number (back INTO the D FF's). Can I somehow do this with the Preset and Clear?

And what about timing? This is all done with a clock.

I know this is probably confusing without seeing a schematic, so I am sorry for that. Any help or suggestions are GREATLY appreciated.

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chroot
Staff Emeritus
Gold Member
kriegsmachine,

Are you required to use the double dabble algorithm for your design? It seems overly complex for this purpose. The binary->BCD converter is just an arbitrary 8-input, 21-output function. It is purely combinational, and you can use something like a Karnaugh map to determine its simplest form.

- Warren

No I am not, but I looked into the Karnaugh map idea and that seemed like I would need far too many chips for it to be practical.

I don't see why I would need 21 outputs. There are 8 inputs, and 4 outputs for each 7-segment display. Thats a total of 12 outputs. Minus the two MSBs on the 100's place display, leaving 10 outputs.

I set up a truth table listing all numbers 0-255 in binary form and used a Java program to simplify them. It wasn't pretty.

Just as an example my 5th output (2's place on 10's 7-seg display) simplified to:

( A'. B'. C'. D . F ) + ( A'. B'. C'. D . E ) + ( B'. C . D'. E') + ( A'. B . C'. D') + ( A'. B . C . D . E ) + ( A . B'. D'. E') + ( A . B'. D'. F') + ( A . B'. C . E'. F') + ( A . C . D') + ( A . B . C'. D . E . F ) + ( A'. B'. D . E . F )

With 'A' being the MSB and 'H' the LSB of the binary input.

Chroot was right that using the Double Dabble approach would be complicated, if conventional thinking is employed; however, some shortcuts may be possible. I’ve noted a couple of possible provisions, using the Double Dabble approach whereby the process appears to become much simpler - - if mapping is carefully used. I’m going to test the ideas to see if they work the way I expect that they will. As an example, it should be noted that a full-fledged comparator isn’t required because you don’t to make general compares. Rather you simply need to find a small number of values greater than a fixed threshold - - perfect for mapping. The same goes for the add. In fact, through proper mapping the add and the compare can just about be combined into something much simpler. I intend to test my observations to see if it is as I expect. I expect to get back with you when I have done so.

KM

berkeman
Mentor
Chroot was right that using the Double Dabble approach would be complicated, if conventional thinking is employed; however, some shortcuts may be possible. I’ve noted a couple of possible provisions, using the Double Dabble approach whereby the process appears to become much simpler - - if mapping is carefully used. I’m going to test the ideas to see if they work the way I expect that they will. As an example, it should be noted that a full-fledged comparator isn’t required because you don’t to make general compares. Rather you simply need to find a small number of values greater than a fixed threshold - - perfect for mapping. The same goes for the add. In fact, through proper mapping the add and the compare can just about be combined into something much simpler. I intend to test my observations to see if it is as I expect. I expect to get back with you when I have done so.

KM
Please keep in mind that this is schoolwork, so if you solve the OP's problem, that would violate the PF rules.

We are allowing this thread to stay in EE for now, because it is project-oriented, but it is still the OP's schoolwork, so s/he must do the bulk of the work. So you can offer hints (as you have done so far), and ask probing questions, and find errors, but please do not post a solution or do the OP's schoolwork for them. Thanks.

berkeman
Mentor
No I am not, but I looked into the Karnaugh map idea and that seemed like I would need far too many chips for it to be practical.

I don't see why I would need 21 outputs. There are 8 inputs, and 4 outputs for each 7-segment display. Thats a total of 12 outputs. Minus the two MSBs on the 100's place display, leaving 10 outputs.

I set up a truth table listing all numbers 0-255 in binary form and used a Java program to simplify them. It wasn't pretty.

Just as an example my 5th output (2's place on 10's 7-seg display) simplified to:

( A'. B'. C'. D . F ) + ( A'. B'. C'. D . E ) + ( B'. C . D'. E') + ( A'. B . C'. D') + ( A'. B . C . D . E ) + ( A . B'. D'. E') + ( A . B'. D'. F') + ( A . B'. C . E'. F') + ( A . C . D') + ( A . B . C'. D . E . F ) + ( A'. B'. D . E . F )

With 'A' being the MSB and 'H' the LSB of the binary input.
Are you allowed to use a PAL or CPLD for the logic implementation? That would make it much more practical (and better practice for you) than implementing this with discrete SSI chips. Can you estimate what size CPLD / FPGA you would need to implement this?

Also, how do you drive a 7-segment display with 4 outputs?

I only have access to 7400 series TTL chips. I have a new idea and I think it will work, but it seems almost too easy.

I plan on loading two stringed 4-bit binary counters with the 8-bit binary. Then counting down on those until zero is reached, meanwhile using 3 decade counters to count up from zero. Each will be connected to the same clock. When the binary counters reach zero, the decade counters will have reached the correct number.

Please keep in mind that this is schoolwork, so if you solve the OP's problem, that would violate the PF rules.

We are allowing this thread to stay in EE for now, because it is project-oriented, but it is still the OP's schoolwork, so s/he must do the bulk of the work. So you can offer hints (as you have done so far), and ask probing questions, and find errors, but please do not post a solution or do the OP's schoolwork for them. Thanks.
Thanks for the "heads up". I certainly don't intend to violate the rules, and will not post answers here - - just possibly suggestions, and how I have progressed. (Actually, I cannot post diagrams here, even if I wanted to.)

KM

berkeman
Mentor
Thanks for the "heads up". I certainly don't intend to violate the rules, and will not post answers here - - just possibly suggestions, and how I have progressed. (Actually, I cannot post diagrams here, even if I wanted to.)

KM
No worries.

kriegs lastest idea seems pretty creative -- what do you think of it? I think there are some init/clocking issues, but they seem to be not too bad. (Like how often to do the init/clocking/latching cycle)

I was thinking of OR-ing together the 8 outputs of the binary counters, so when they all reach zero the output of the OR gate is zero. Take that signal and AND it with the clock pulses and we have a stopping mechanism.

I'm going to try my ideas later, so I will post the results sometime soon.

All set. I built my idea, only took about 30 minutes and it works perfectly. I just cranked up the clock speed to 10 kHz so the display updates seemingly instantly. Thanks for the help everyone.

No worries.

kriegs lastest idea seems pretty creative -- what do you think of it? I think there are some init/clocking issues, but they seem to be not too bad. (Like how often to do the init/clocking/latching cycle)
Very clever. Rather than trying to convert, just recount the value. It will definitely work, though I'm not exactly sure what the instructor might think of it. Imagine the time to convert 32-bit numbers.

By the way; I tested what I described earlier and it works perfectly (after numerous assembly miscues have been solved). By mapping, a direct converter is constructed, which eliminates almost all of the adder and comparator circuitry; it only requires mapping using truth tables derived from the initial count list to the intended (add three) count list. I would suggest that kriegsmachine look through https://www.physicsforums.com/showthread.php?t=100628".

KM

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Are you allowed to use the full range of 7400 series devices or are you restricted to using certain ones?