Crushforce
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Designing a 2-bit full adder using nothing but NAND gates?
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I don't see how. Check your Cout, however. If b1 is zero, your carry is always on.
ISamson
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Does it do addition? Is that what you mean by 'adder'?
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Crushforce
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Yeah I just realized that, how about this?mfb said:
While that is a 2-bit adder it is designed with gates other than NAND. Granted I could simply replace each gate with the NAND equivalent, I kinda want to make this with the least amount of gates possible. Which is why I have come to this forum to see if I can get this simplified as much as possible.Svein said:
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Are you familiar with Karnaugh diagrams? ( https://en.wikipedia.org/wiki/Karnaugh_map )Crushforce said:
Crushforce
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Slight update there should be a not gate where it says "carry-out"
Somewhat... but not entirely. I've seen them online but I have no formal experience other than reading them.Svein said:
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I asked because a Karnaugh map is used for minimizing logical expressions with respect to gates.Crushforce said:
Anyhow - check out https://en.wikipedia.org/wiki/Adder_(electronics) .
jerromyjon
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I think the main point was to use only NAND gates since they can perform the function of any gate...
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Yes, You use the kmap to get the minimum logical expression, you then convert them to nand gates. You can also use the kmap and OLNY find nand gate connectionsjerromyjon said:
jerromyjon
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Sorry, I skimmed and missed that point. And thank you that saves some brain strain!donpacino said:
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Happens to the best of usjerromyjon said:
Crushforce said:
A good way to organize this in the future, make a block consisting of 2 inputs, 1 carry in bit, 1 output, and 1 carry out.
This will then scale to any number of bits. you just attach the carry out from one to the carry in from another. Then if you want to optimize, remove the carry in section from your first bit (although in a real system you might need it).
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Your design is for a 1 bit half adder followed by a 1 bit full adder.Crushforce said:
A two bit adder needs a carry input to make it a “full” adder.
Your solution, 4 inputs; in decimal, 3+3 = 6; which needs three outputs.
A full adder, 5 inputs; in decimal, 1+3+3 = 7; which also needs three outputs.
We need to know the rules of the challenge, what is the target technology?
Is there a carry input to the first stage?
Is the design restricted to using NAND gates only?
Can gates with three or more inputs be used?
Crushforce
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Baluncore said:
1) We need to know the rules of the challenge, what is the target technology?
-There is no target tech, simply creating it using 7400 integrated circuits on a bread board.
2) Is there a carry input to the first stage?
-I'll get back to you on this.
3)Is the design restricted to using NAND gates only?
-Yes
4)Can gates with three or more inputs be used?
-No
Sorry I cannot reply to everyone, I've gotten a bit busy. I am still reading what people have to say though.
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When only NAND gates with two inputs are used, the fundamental 3-input EXOR gates and 3-input MAJority gates can be constructed. Each pair of those 3-input gates makes a one bit slice of full adder with ripple carry, in and out.
A two bit full adder can be made using 4 of those constructed 3-input gates.
A total of 28 primitive 2-input NAND gates are needed.
That can be reduced to 26 since one NAND gate is duplicated between the EXOR and MAJ gates.
The 74x00 chip is a Quad 2-input NAND gate. There is an alternative quad 2-input NAND that has open-collector outputs, which can be used for negative-logic wired-OR, the 74x01. It would reduce the total gate count, which is why it was quickly introduced, immediately after the 74x00.
There is a trick that can generate carry from the three input EXOR gate without need for the MAJ gate. Here is my two bit full adder, with carry in and out, that seems to work, but needs only 18 primitive NAND gates.
A two bit full adder can be made using 4 of those constructed 3-input gates.
A total of 28 primitive 2-input NAND gates are needed.
That can be reduced to 26 since one NAND gate is duplicated between the EXOR and MAJ gates.
The 74x00 chip is a Quad 2-input NAND gate. There is an alternative quad 2-input NAND that has open-collector outputs, which can be used for negative-logic wired-OR, the 74x01. It would reduce the total gate count, which is why it was quickly introduced, immediately after the 74x00.
There is a trick that can generate carry from the three input EXOR gate without need for the MAJ gate. Here is my two bit full adder, with carry in and out, that seems to work, but needs only 18 primitive NAND gates.
Code:
c1 ' carry input, bit value 1
a1, b1 ' data inputs, bit value 1
a2, b2 ' data inputs, bit value 2
c2 ' internal carry, bit value 2
s1, s2, s4 ' sum output terms, s4 is carry out
t11 = NAND( a1, b1 )
t12 = NAND( t11, b1 )
t13 = NAND( a1, t11 )
t14 = NAND( t12, t13 )
t15 = NAND( c1, t14 )
t16 = NAND( t14, t15 )
t17 = NAND( c1, t15 )
s1 = NAND( t16, t17 ) ' sum, bit value 1
c2 = NAND( t11, t15 ) ' internal carry
t21 = NAND( a2, b2 )
t22 = NAND( t21, b2 )
t23 = NAND( a2, t21 )
t24 = NAND( t22, t23 )
t25 = NAND( c2, t24 )
t26 = NAND( t24, t25 )
t27 = NAND( c2, t25 )
s2 = NAND( t26, t27 ) ' sum, bit value 2
s4 = NAND( t21, t25 ) ' sum or carry out, bit value 4
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Vitro
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@Crushforce, I think you just need one more NAND in the diagram from post 5 to invert the carry from bit 0, so you'll need 14 gates total for your 2-bit adder. But this is not a full 2-bit adder because it doesn't have a carry in, your bit 0 is a half adder, so you can't chain them to make an arbitrary length adder. That's ok though if you only need two bits and want to minimize the number of gates used.