Designing a UART Counter for Receiver Unit

[EvLer]

This is a UART problem, we need to design a counter for the receiver unit. And the specs go like this:
system clock is 20 MHz, while data arival frequency is 2MHz, also I need to assert a STOP_RECEIVING signal once all data is received. And of course, data has a start bit and a stop bit. And assume that there is a signal saying start bit detected. Also after a bit is received, I need to assert a strobe signal, i.e. for each bit. Data arrives asynchronously but is synchronized using 2 FFs.

So, here's my thinking thread:
it will take 10 system clock cycles to get through the start bit and 5 cycles to sample the first bit. After that i need to count only 10 cycles to sample the following bit, and I need to count the bits received.
I think i get the idea... BUT i run into problems with implemeting it... i can count the clock cycles ... state machine basically... then i reset the counter... but how would I count the bits? An embedded state machine sounds too much...
if someone could walk me through the high-level part of this, i would really appreciate it...

 

[berkeman]

You can embed a synchronous counter block in your circuit. Check out the description of synchronous counters in your textbook, or at wikipedia:

http://en.wikipedia.org/wiki/Counter