Digital logic excitation equation from state diagram?

[orangeincup]

Homework Statement

Design serial transmitter circuit take 8-bit word in parallel as input, when an input control signal (SEND) goes high, and serially outputs the word (i.e., one bit during each clock cycle) to a single transmission line. Transmission of a word begins with the least significant bit, preceded by a high "start" bit and terminated by at least two low "stop" bits.

The transmission line should have a low signal level, until the start of the transmission of an 8-bit word (as indicated by the start bit which is a high level). Note that each word on the transmission line must be separated by at least two bit times of low (i.e., the stop bits), prior to the arrival of the next start bit. You may assume that SEND is set low prior to the completion of the transmission and re-asserted when the next data word is available to transmit.

Homework Equations

The Attempt at a Solution

So I designed this state diagram with 3 states

IDLE->LOAD->TRANSMIT

Idle returns to idle if send is 0, idle goes to load if send is 1
transmit goes to transmit if bit count isn't 10, goes to done if bit count is 10
done returns to idle

So I want to make an actual circuit of this but I don't know how to create the kmaps for it

So far I have
idle=000
load=10
transmit=01

 

[donpacino]

a kmap handles real time logic, not memory.

you have three states, how many bits will you need to represent the states?? (hint you basically have this already)
each bit will be represented by the output of a flip flop (if you're using discrete logic chips).
you can then use the flip flop outputs as your states.
using your system inputs and your state inputs (flip flop output) you can make your kmap.at what level does this have to be done?
can it be done with vhdl, or does it have to be done using discrete logic chips?
Can you only use basic gates, or can you use more complicated devices?
do you really have to load the data into a fifo?
do you have to make your own fifo?