Digital logic excitation equation from state diagram?

In summary, the conversation discusses the design of a serial transmitter circuit that takes an 8-bit word in parallel as input and outputs it serially to a transmission line. The circuit includes a start bit, at least two stop bits, and uses a state diagram with three states (IDLE, LOAD, and TRANSMIT). The output will be represented by flip flop outputs and the circuit can be created using basic gates or more complicated devices. The need for a FIFO and whether it can be done with VHDL is also discussed.
  • #1
orangeincup
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Homework Statement


Design serial transmitter circuit take 8-bit word in parallel as input, when an input control signal (SEND) goes high, and serially outputs the word (i.e., one bit during each clock cycle) to a single transmission line. Transmission of a word begins with the least significant bit, preceded by a high "start" bit and terminated by at least two low "stop" bits.

The transmission line should have a low signal level, until the start of the transmission of an 8-bit word (as indicated by the start bit which is a high level). Note that each word on the transmission line must be separated by at least two bit times of low (i.e., the stop bits), prior to the arrival of the next start bit. You may assume that SEND is set low prior to the completion of the transmission and re-asserted when the next data word is available to transmit.

Homework Equations

The Attempt at a Solution


So I designed this state diagram with 3 states

IDLE->LOAD->TRANSMIT

Idle returns to idle if send is 0, idle goes to load if send is 1
transmit goes to transmit if bit count isn't 10, goes to done if bit count is 10
done returns to idle

So I want to make an actual circuit of this but I don't know how to create the kmaps for it

So far I have
idle=000
load=10
transmit=01
 
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  • #2
a kmap handles real time logic, not memory.

you have three states, how many bits will you need to represent the states?? (hint you basically have this already)
each bit will be represented by the output of a flip flop (if you're using discrete logic chips).
you can then use the flip flop outputs as your states.
using your system inputs and your state inputs (flip flop output) you can make your kmap.at what level does this have to be done?
can it be done with vhdl, or does it have to be done using discrete logic chips?
Can you only use basic gates, or can you use more complicated devices?
do you really have to load the data into a fifo?
do you have to make your own fifo?
 

Related to Digital logic excitation equation from state diagram?

1. What is a digital logic excitation equation?

A digital logic excitation equation is a mathematical expression that describes the behavior of a digital logic circuit based on its state diagram. It takes into account the current state and inputs of the circuit to determine the next state and outputs.

2. How is a digital logic excitation equation derived from a state diagram?

The digital logic excitation equation is derived by analyzing the state diagram of the circuit and determining the logic conditions that must be satisfied for each transition from one state to another. These conditions are then combined into a Boolean expression, which forms the excitation equation.

3. What is the purpose of a digital logic excitation equation?

The purpose of a digital logic excitation equation is to provide a systematic and formal method for designing and analyzing digital logic circuits. It allows engineers to predict the behavior of a circuit and ensure that it meets the desired specifications.

4. How is a digital logic excitation equation used in circuit design?

The digital logic excitation equation is used in circuit design to determine the appropriate logic gates and connections needed to implement the desired behavior. It also helps in identifying any potential hazards or glitches that may occur in the circuit.

5. Can a digital logic excitation equation be used for any type of circuit?

Yes, a digital logic excitation equation can be used for any type of digital logic circuit, regardless of its complexity. It is a fundamental tool in digital circuit design and analysis and is applicable to both simple and complex circuits.

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