Designing Asynchronous Up-Down Counter w/ SN 7474

[munkachunka]

Hi there, I am working my way through some past exam papers and am stuck on this question, the answer that was given to me with the past exam was wrong so I have no reference, I cannot find anywhere on the net or in books the type of cct I am trying to design.

In previous parts of the question I have drawn the cct diagrams for an Up-counter and a down counter using 3 SN 7474 D type flip-flops. The only difference between the ccts being where the feedback is taken from, I.e Q or Not Q.

The question is "there is a requirement to either clear all Q outputs or present them to 1 witht the input clock to the first stage (flipflop A) stopped. Include suitable switches and Logic dates, draw the diagram for the complete Up-down counter.

I think I need to attach the IP/s of Set and Reset to a switch which would either set or reset the switch when the OP goes low, this would be done using a not gate to reset.

I am not sure how to integrate the up and down counters together, The only counters that I can find similar to this use J/K's.

Any help would be appreciated.

 

[Jonno]

If you have a switch that provides a logic '0' to change the counter from up to down then try come up with the boolean expression for the clock inputs Bistables B and C.

The clock inputs of the Bistable B is driven by the ouput of Bistbale A. Q to up count and not Q to down count. What you need is a few gates in between the Q and not Q outputs and the D input of the next Bistable.

Hope that makes sense but having just spent an hour or so on this very problem I'm hesitnent to give the answer straight to you.

See you in March (maybe)