- #1
arhzz
- 279
- 56
- Homework Statement
- Find the differential gain
- Relevant Equations
- -
Hello; (this is going to be lengthy post)
So im trying to find the small signal differential gain of this circuit
The input is at the 2 NMOS's above the degeneration resistor and the output is where the capacitors are hanging (excuse that I didnt label them, the program where I drew the circuit doesnt have that option).
My approach was divide and conquer; I first wanted to look only at the "core" part of the circuit (excluding the Push-pull stage) and find the diff. gain of that part and than combine it all together;
This is the core part of the circuit
You notice that this has external biasing for the bottom two transistors that create a current mirror. This is not included in the original circuit since I wanted to preserve readibilty; but basically im biasing with an ideal current source with a diode connected NMOS. An equivalent, but simpler circuit is this
The bottom two NMOS transistors are as ideal current sources. The reason I prefer the core circuit to look like this is since something rather similar can be found in the book of Razhavi (design of analog CMOS circuits) and I have been able to understand how he tackles problems similar to this.
My simulation of the circuit has shown that I have perfecty symmetry so I opted to use the half circuit technique described in the Razhavi book. I just look at one side of the circuit and calculate the gain; the total gain is just that times 2.
So thats what I did; The top diode connected PMOS active load will act as an resistor with an value 1/gm (we neglect gds since it is significantly smaller) the current source will go to a virtual ground (explained in Razhavi) and the degeneration resistor will be "split" to Rs/2 on both sides.
Than we do the small signal analysis (if needed I can post the circuit diagramm) and I get the following result;
$$ \frac{Vout}{Vin} = \frac{-gm_N}{gm_P(1+\frac{gm_NRS}{2})} $$
where ## gm_N ## is the gm of the NMOS in the middle and ## gm_P ## the transcondutance of the diode connected PMOS
Now this is where I get stuck; I cannot incorporate the push-pullstage. I am not sure if I should draw the push pull stage seperatly and simplify as much as possible and add to my existing core circuit or do I have to do it in one swoop so to say?
Any insights?
Also what do you think of my plan to do the small signal analysis? And how is this looking so far.
Excuse the lengthy post and thanks in advance!
So im trying to find the small signal differential gain of this circuit
The input is at the 2 NMOS's above the degeneration resistor and the output is where the capacitors are hanging (excuse that I didnt label them, the program where I drew the circuit doesnt have that option).
My approach was divide and conquer; I first wanted to look only at the "core" part of the circuit (excluding the Push-pull stage) and find the diff. gain of that part and than combine it all together;
This is the core part of the circuit
You notice that this has external biasing for the bottom two transistors that create a current mirror. This is not included in the original circuit since I wanted to preserve readibilty; but basically im biasing with an ideal current source with a diode connected NMOS. An equivalent, but simpler circuit is this
The bottom two NMOS transistors are as ideal current sources. The reason I prefer the core circuit to look like this is since something rather similar can be found in the book of Razhavi (design of analog CMOS circuits) and I have been able to understand how he tackles problems similar to this.
My simulation of the circuit has shown that I have perfecty symmetry so I opted to use the half circuit technique described in the Razhavi book. I just look at one side of the circuit and calculate the gain; the total gain is just that times 2.
So thats what I did; The top diode connected PMOS active load will act as an resistor with an value 1/gm (we neglect gds since it is significantly smaller) the current source will go to a virtual ground (explained in Razhavi) and the degeneration resistor will be "split" to Rs/2 on both sides.
Than we do the small signal analysis (if needed I can post the circuit diagramm) and I get the following result;
$$ \frac{Vout}{Vin} = \frac{-gm_N}{gm_P(1+\frac{gm_NRS}{2})} $$
where ## gm_N ## is the gm of the NMOS in the middle and ## gm_P ## the transcondutance of the diode connected PMOS
Now this is where I get stuck; I cannot incorporate the push-pullstage. I am not sure if I should draw the push pull stage seperatly and simplify as much as possible and add to my existing core circuit or do I have to do it in one swoop so to say?
Any insights?
Also what do you think of my plan to do the small signal analysis? And how is this looking so far.
Excuse the lengthy post and thanks in advance!
