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Digital Logic - Tri State Buffers

  1. Feb 8, 2014 #1
    1. The problem statement, all variables and given/known data

    I'm trying to implement the function

    F = A'BC+ABD+AB'D'

    using 3 tri-state buffers. Apparently I'm supposed to connect the buffers together and use C, D, and D' as inputs to buffers. I'm supposed to pass A and B through logic to get the input signals. I'm supposed to additional logic.

    2. Relevant equations



    3. The attempt at a solution

    Since I'm not given any other restrictions I made the following circuit

    http://imageshack.com/a/img703/7883/np43.png [Broken]

    This gives me the correct truth table for the function except for

    0000
    0001
    0010
    0011
    0100

    I get Z, otherwise for all of the other input combinations I get the same outputs as the function. I'm not exactly sure if I'm doing something wrong or need to change somethings around but I'm seem to be stuck.

    Thanks for any help.
     
    Last edited by a moderator: May 6, 2017
  2. jcsd
  3. Feb 8, 2014 #2

    mfb

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    2016 Award

    Staff: Mentor

    I think they are needed to set one of the buffers to zero. I'm not sure why you get exactly those 5 states with an undefined output.
     
  4. Feb 8, 2014 #3

    NascentOxygen

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    Staff: Mentor

    Hi GreenPrint. I'm as new to tri-state buffers as you are, so accept my advice with caution.

    First, I think we'd agree that at all times, one and only one buffer must be active and feeding a logic level to the output. I can see you take care of the case where A and B are both HIGH, and where A is LOW and B is HIGH (viz, A'B), and also the third case AB'. But what happens when A is LOW and B also is LOW? You haven't accounted for that occurrence, so when it happens there will be trouble, because no buffer will be feeding any signal to the common output.

    So, I'd say you need another tri-state buffer, one that becomes active when none of the of these 3 is active. What logic signal should it deliver to the common output at this time? Certainly not a logic HIGH, that would change the function you are implementing. But feeding a logic LOW won't upset anything.

    * EDIT: I'll amend that. No need for a 4th tri-state buffer, you can arrange for one of the three you are using to be enabled for two logic conditions (the one you currently use, plus A'B') and this means you will need fewer logic gates than you show above.

    See how you go with that, and report back. There may be something more I haven't considered. *
     
    Last edited: Feb 9, 2014
  5. Feb 9, 2014 #4

    rude man

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    One and only one of the tri-state buffers must be enabled. "Enabled" means the output is active high or low. The other two buffers must be in the third (high-impedance) state.
     
  6. Feb 9, 2014 #5

    CWatters

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    This isn't at all clear. Is the above part of the problem statement or just one solution to the problem?

    What's the difference between "input to buffers" and "input signals" ?

    Are you allowed a pull up resistor?
     
  7. Feb 9, 2014 #6

    CWatters

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    If you are allowed a pull up resistor then..

    If you connect the input of each buffer to it's own enable (active low) then you can build a "wired AND" gate. However I believe you would need an inverter after the buffers.

    F = (A'.B.C)+(A.B.D)+(A.B'.D')
    = ((A'.B.C)+(A.B.D)+(A.B'.D'))''
    = ((A'.B.C)'.(A.B.D)'.(A.B'.D')')'

    although this might not be in the spirit of the problem.
     
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