Digital Logic - Tri State Buffers

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Discussion Overview

The discussion revolves around implementing a specific logic function using tri-state buffers. Participants explore how to connect the buffers and manage the inputs to achieve the desired output while addressing potential issues with undefined states in the truth table.

Discussion Character

  • Homework-related
  • Technical explanation
  • Debate/contested

Main Points Raised

  • One participant describes their attempt to implement the function F = A'BC + ABD + AB'D' using three tri-state buffers, noting that their circuit produces undefined outputs for specific input combinations.
  • Another participant suggests that the buffers must be connected in a way that ensures only one buffer is active at a time, highlighting the need to account for all possible input combinations.
  • A third participant proposes that an additional tri-state buffer may be necessary to handle cases where both A and B are LOW, suggesting it should output a logic LOW to avoid altering the function.
  • There is a question about the clarity of the problem statement regarding the inputs to the buffers and whether a pull-up resistor is allowed, indicating some confusion about the requirements.
  • One participant discusses the possibility of using a pull-up resistor and describes a method to create a "wired AND" gate using the enable signals of the buffers, although they express uncertainty about whether this approach aligns with the problem's intent.

Areas of Agreement / Disagreement

Participants generally agree on the importance of ensuring only one buffer is enabled at a time, but there is no consensus on the exact configuration needed to achieve the desired output or whether additional components are necessary.

Contextual Notes

Participants express uncertainty regarding the problem statement and the use of pull-up resistors, which may affect the implementation of the logic function. There are also unresolved questions about the handling of specific input combinations leading to undefined outputs.

GreenPrint
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Homework Statement



I'm trying to implement the function

F = A'BC+ABD+AB'D'

using 3 tri-state buffers. Apparently I'm supposed to connect the buffers together and use C, D, and D' as inputs to buffers. I'm supposed to pass A and B through logic to get the input signals. I'm supposed to additional logic.

Homework Equations





The Attempt at a Solution



Since I'm not given any other restrictions I made the following circuit

http://imageshack.com/a/img703/7883/np43.png

This gives me the correct truth table for the function except for

0000
0001
0010
0011
0100

I get Z, otherwise for all of the other input combinations I get the same outputs as the function. I'm not exactly sure if I'm doing something wrong or need to change somethings around but I'm seem to be stuck.

Thanks for any help.
 
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Apparently I'm supposed to connect the buffers together and use C, D, and D' as inputs to buffers.
I think they are needed to set one of the buffers to zero. I'm not sure why you get exactly those 5 states with an undefined output.
 
Hi GreenPrint. I'm as new to tri-state buffers as you are, so accept my advice with caution.

First, I think we'd agree that at all times, one and only one buffer must be active and feeding a logic level to the output. I can see you take care of the case where A and B are both HIGH, and where A is LOW and B is HIGH (viz, A'B), and also the third case AB'. But what happens when A is LOW and B also is LOW? You haven't accounted for that occurrence, so when it happens there will be trouble, because no buffer will be feeding any signal to the common output.

So, I'd say you need another tri-state buffer, one that becomes active when none of the of these 3 is active. What logic signal should it deliver to the common output at this time? Certainly not a logic HIGH, that would change the function you are implementing. But feeding a logic LOW won't upset anything.

* EDIT: I'll amend that. No need for a 4th tri-state buffer, you can arrange for one of the three you are using to be enabled for two logic conditions (the one you currently use, plus A'B') and this means you will need fewer logic gates than you show above.

See how you go with that, and report back. There may be something more I haven't considered. *
 
Last edited:
One and only one of the tri-state buffers must be enabled. "Enabled" means the output is active high or low. The other two buffers must be in the third (high-impedance) state.
 
Apparently I'm supposed to connect the buffers together and use C, D, and D' as inputs to buffers. I'm supposed to pass A and B through logic to get the input signals.

This isn't at all clear. Is the above part of the problem statement or just one solution to the problem?

What's the difference between "input to buffers" and "input signals" ?

Are you allowed a pull up resistor?
 
If you are allowed a pull up resistor then..

If you connect the input of each buffer to it's own enable (active low) then you can build a "wired AND" gate. However I believe you would need an inverter after the buffers.

F = (A'.B.C)+(A.B.D)+(A.B'.D')
= ((A'.B.C)+(A.B.D)+(A.B'.D'))''
= ((A'.B.C)'.(A.B.D)'.(A.B'.D')')'

although this might not be in the spirit of the problem.
 

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