Digital Logic - Tri State Buffers

  • Thread starter GreenPrint
  • Start date
  • #1
1,196
0

Homework Statement



I'm trying to implement the function

F = A'BC+ABD+AB'D'

using 3 tri-state buffers. Apparently I'm supposed to connect the buffers together and use C, D, and D' as inputs to buffers. I'm supposed to pass A and B through logic to get the input signals. I'm supposed to additional logic.

Homework Equations





The Attempt at a Solution



Since I'm not given any other restrictions I made the following circuit

http://imageshack.com/a/img703/7883/np43.png [Broken]

This gives me the correct truth table for the function except for

0000
0001
0010
0011
0100

I get Z, otherwise for all of the other input combinations I get the same outputs as the function. I'm not exactly sure if I'm doing something wrong or need to change somethings around but I'm seem to be stuck.

Thanks for any help.
 
Last edited by a moderator:

Answers and Replies

  • #2
34,465
10,585
Apparently I'm supposed to connect the buffers together and use C, D, and D' as inputs to buffers.
I think they are needed to set one of the buffers to zero. I'm not sure why you get exactly those 5 states with an undefined output.
 
  • #3
NascentOxygen
Staff Emeritus
Science Advisor
9,244
1,072
Hi GreenPrint. I'm as new to tri-state buffers as you are, so accept my advice with caution.

First, I think we'd agree that at all times, one and only one buffer must be active and feeding a logic level to the output. I can see you take care of the case where A and B are both HIGH, and where A is LOW and B is HIGH (viz, A'B), and also the third case AB'. But what happens when A is LOW and B also is LOW? You haven't accounted for that occurrence, so when it happens there will be trouble, because no buffer will be feeding any signal to the common output.

So, I'd say you need another tri-state buffer, one that becomes active when none of the of these 3 is active. What logic signal should it deliver to the common output at this time? Certainly not a logic HIGH, that would change the function you are implementing. But feeding a logic LOW won't upset anything.

* EDIT: I'll amend that. No need for a 4th tri-state buffer, you can arrange for one of the three you are using to be enabled for two logic conditions (the one you currently use, plus A'B') and this means you will need fewer logic gates than you show above.

See how you go with that, and report back. There may be something more I haven't considered. *
 
Last edited:
  • #4
rude man
Homework Helper
Insights Author
Gold Member
7,780
766
One and only one of the tri-state buffers must be enabled. "Enabled" means the output is active high or low. The other two buffers must be in the third (high-impedance) state.
 
  • #5
CWatters
Science Advisor
Homework Helper
Gold Member
10,529
2,296
Apparently I'm supposed to connect the buffers together and use C, D, and D' as inputs to buffers. I'm supposed to pass A and B through logic to get the input signals.
This isn't at all clear. Is the above part of the problem statement or just one solution to the problem?

What's the difference between "input to buffers" and "input signals" ?

Are you allowed a pull up resistor?
 
  • #6
CWatters
Science Advisor
Homework Helper
Gold Member
10,529
2,296
If you are allowed a pull up resistor then..

If you connect the input of each buffer to it's own enable (active low) then you can build a "wired AND" gate. However I believe you would need an inverter after the buffers.

F = (A'.B.C)+(A.B.D)+(A.B'.D')
= ((A'.B.C)+(A.B.D)+(A.B'.D'))''
= ((A'.B.C)'.(A.B.D)'.(A.B'.D')')'

although this might not be in the spirit of the problem.
 

Related Threads on Digital Logic - Tri State Buffers

Replies
1
Views
759
  • Last Post
Replies
0
Views
2K
  • Last Post
Replies
5
Views
737
  • Last Post
Replies
10
Views
8K
  • Last Post
Replies
2
Views
620
  • Last Post
Replies
3
Views
15K
  • Last Post
Replies
3
Views
1K
  • Last Post
Replies
5
Views
616
Replies
4
Views
1K
Replies
3
Views
1K
Top