Designing a Parity Bit Circuit for Data Transmission

[thercias]

Homework Statement

A parity bit will be 0 if the data contains an
even number of 1’s and it will be 1 if the data contains an odd number of 1’s. If during
transmission a 1 is changed to a 0 or vice versa, then the parity check at the receiver will
fail. Determine the parity P for
4–bits of data, A, B, C, and D. You should
Determine the truth table, Karnough Map, and logical expression for P. Draw the circuit that executes the logic. Simplify the circuit to a minimum number of logic gates.

Homework Equations

The Attempt at a Solution

Would the solution just be an even parity? In that case.

Truth Table: Since it is 0 with an even number 1s, and 1 if it will has an odd number of 1s
4-bit | Parity
0000 0
0001 1
0010 1
0011 0
0100 1
0101 0
0110 0
0111 1
1000 1
1001 0
1010 0
1011 1
1100 0
1101 1
1110 1
1111 0

Karnough Map:
For AB on the column and CD on the row

-----00 01 11 10
00--0--1---0---1
01--1--0--1----0
11--0--1--0----1
10--1--0--1---0

Logical Expression:
P =A ⊕ B ⊕ C ⊕ D

Never really been taught how to come up with the circuit diagram though. Any help?

 

[CWatters]

Perhaps start with the logic symbol for a ⊕ gate?