Eddy currents in an Aluminum substrate PCB

[Rive]

TL;DR Summary

Resource request about effects of eddy currents in an Al substrate PCB

Well, then: my first real topic here on PF

We will soon do a half-bridge PWM thing, if everything goes smoothly.
Bit of a scary thing, actually.

So far it's about gathering reference material and examples. Even the simulations are just in planning phase. But: as it seems the dissipation on the switching elements wants to climb out of budget as the gathered material got sorted and re-calculated to our case.

Of course there are several ways to mitigate this, but since we have some previous matters with AL substrate PCBs, it got priority. At least, for me.
However, I have no experience (and luck with finding reference materials about this topic) with the high frequency, high current loop of the gate control. Since the substrate is solid metal (well... Aluminium counts so, maybe 😝) eddy currents seems to be a potential problem. Can somebody suggest some reference material about this?

Target frequency is about 50kHz and I intend to push it up till 200kHz during some experiments.
MOSFETs will be general modern SiC MOS device, with a good beefy driver.

 

[berkeman]

Can you post a schematic and a sketch of the mechanical arrangement? Which FETs are you using, and how are they heat sinked? Is there forced air cooling (like with a fan), or is it all convective cooling? More details will help us help you better.

Also, are you familiar with how to cut up planes to mitigate eddy current losses?

 

[Rive]

It is still about reference gathering, so I don't have much any of that. Cooling will depend on necessity: the switching element is preferred to be some type of SMD, with heat pad soldered to the PCB.
Maybe we can go with one of the reference designs
The plan is to do more or less the 'core' of this design, but on IMS.

I could find designs with IMS (like the power board of this one or https://powerpulse.net/3-phase-1-25kw-200vac-gan-inverter-reference-design-for-integrated-drives/), but so far nothing with the gate driver on the same PCB: also nothing really specific the design of the gate driver on IMS.

Plane cutting - I will have no plane on IMS to cut. Needs to be single layer and I cannot cut the IMS itself.

 

[berkeman]

Interesting. Do they mention eddy current issues in your links? So far I'm not seeing that...

From your 2nd link:

 

[Rive]

Interesting. Do they mention eddy current issues in your links? So far I'm not seeing that...

It's me who is worrying about that... And not finding references. Just like that document: parasitic inductance/capacitance is there, but (maybe because they have the driver on a separate PCB?) they did not mention anything about eddy currents/losses due the substrate.

Maybe I'm just overthinking this.

 

[Tom.G]

This thread may shine a little light on the subject:

https://www.physicsforums.com/threads/pcb-traces-are-overheating-due-to-eddy-currents.974540/

 

[essenmein]

Wouldn't worry about it unless you are talking many MHz, if not 100's of MHz continuous wave type signals. In a 50 or even 200kHz converter the fundamental is quite low with fast switch transitions. Not sure what voltage level you are working on but I played (most people call it working) with 650 and 1200V GaN and SiC power modules for automotive power train. All of them are bare die on direct bond copper substrate so have similar dead "back metal" and are normally soldered or sintered to a solid metal heatsink.

Loop inductances in both the gate and switch current paths are critical and a curious thing about these eddy currents is that what they actually do is burn off the energy stored in the mag field that slices through this material. Now both copper and aluminium are non magnetic, so they are not changing the flux densities or are in any way affecting the flux paths at DC fields. Since the circuit time constants are so short, the 50 or 200kHz currents are essentially DC while the device is "ON" then you have a 50ns event (turn on or off) where the magnetic field needs to go away or get created very quickly, normally this generates a voltage, however the since a portion of this field is inside a conductive material, rapid change here also generates voltages in this material which cause the eddy currents which then basically burn off that portion of energy. Another way to look at it would be that the gate loop or the current loop forms a coupled inductor with a poor coupling factor with the metal below it, this inductor basically has a shorted turn. Long story short, these eddy current tend to reduce the apparent inductance of the circuit since the portion of energy stored in the mag field in the conductive material is not returned to the circuit when the field collapses.

There are other more nasty problems with SiC/GaN though due to the enormous dV/dt they are capable of, namely your HS gate isolate power supply and gate drives need to handle 10's of kV per us.

 

[Rive]

Thank you very much, it is really informative.

Not sure what voltage level you are working on but I played (most people call it working) with 650 and 1200V GaN and SiC power modules for automotive power train.

It'll be just one class lower. Nasty thing, even that... Don't want any slip-ups, so I rather check every reference I can dig up and track down any possible weak point I can think of.