FPGA-Based System Design with Multiplexed Ring Oscillators

[elayaraja]

Hello Sir,
I am PG scholar in VLSI design.I am doing my project on FPGA based system in that i have to used ring oscillator.From number oscillator i need to choose two oscillator based on multiplexer.Can anyone tell me how it is?

 

[Baluncore]

As I understand the question, you have two asynchronous oscillators and must dynamically select one of those two as the clock.

I assume both oscillators run continuously. When switching between two asynchronous oscillators you must guarantee that the time of the 0 and 1 states of the output are not reduced below that of either oscillator.

See attachment.
The upper diagram shows the theory of how to stop and hold the clocks when high, after the positive edge. The OR gates followed by the AND gate make the data selector controlled by A/B.

BUT, we must also make sure that the first clock has stopped before connecting the second clock. That requires more logic as shown in the second diagram.

I seem to remember something like this from the 1980s, but I cannot find my old documentation.
WARNING, I have not tested or simulated this logic. It may be wrong. You must test it.

 

[Baluncore]

See this link...
http://www.design-reuse.com/articles/5827/techniques-to-make-clock-switching-glitch-free.html