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FPGA VHDL tristate buffer for ram inout signal

  1. Apr 28, 2009 #1
    First off, this is not school related as my semester just ended and I've just been playing around with my fpga.

    My problem is that i'm trying to write to the ram module then read from it. I understand a little of the tristate buffer and inout signal but we didn't really go over this in class and I don't know if what i have is right or wrong. Here is some of my code that should give an indication of everything. (Please note i took out a lot of irrelevant code below for space and simplicity.

    EDIT: I forgot to mention that I read that tristate buffers can only be used with external pins (mine is external ram). Also I just realized that this should probably be better off in the programming section so moving it is no problem.

    1. Is the inout signal correct for the data being sent in(writing ram) when en = '1' and data coming out (reading ram) at en = '0'?
    2. Is the buffer below correct if DQout is the incoming data I want to write to ram, and DQ is the incoming data back (read) when en goes low the data out is DQ.

    Thanks for any help!


    port(
    DQ : inout std_logic_vector(15 downto 0);
    A : out STD_LOGIC_VECTOR(22 downto 0);

    FlashCE_L,CE_L,WE_L,LB_L,OE_L,UB_L,RamCLK,RamADV_L,RamCRE : out STD_LOGIC
    );

    --buffer
    DQout <= DQin when en = '1' else (others => 'Z');

    DQ <= DQin;
     
  2. jcsd
  3. Apr 28, 2009 #2
    Just figured it all out. Thanks anyway, feel free to close the thread or comment if interested.
     
  4. Apr 30, 2009 #3
    Please tell me how you did it because i have the same problem and can't figure it out. Have nice day
     
  5. Apr 30, 2009 #4
    Basically it is the same as I put above. The DQin is the data you want to write and then DQout is the data you want to read when en is '1'.
     
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