Frame Synchronisation via Modified Approach to Bit Insertion

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SUMMARY

The discussion focuses on achieving frame synchronization in a voice transmission project using TTL IC components such as 74HC00 NAND gates and 74HC297 DPLL. The user proposes a modified bit stuffing approach by altering the least significant bit (LSB) of n-bit codewords to minimize false frame detection. The implementation of this solution is questioned, along with methods for identifying and modifying the LSB. The final solution involved using a verifier at the receiver side to filter out false frames effectively.

PREREQUISITES
  • Understanding of TTL IC components, specifically 74HC series
  • Knowledge of bit stuffing techniques in data transmission
  • Familiarity with frame synchronization concepts
  • Experience with PCM codecs, such as TP3054/TP3057
NEXT STEPS
  • Research "TTL IC 74HC series applications" for practical implementations
  • Learn about "Manchester encoding" and its applications in synchronization
  • Explore "Group Coding (4-to-5 bit encoding)" for efficient data transmission
  • Investigate methods for "frame marker detection" and error correction techniques
USEFUL FOR

Electrical engineers, embedded systems developers, and anyone involved in digital communication systems seeking to enhance voice transmission reliability and frame synchronization techniques.

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Homework Statement



I am currently embarking on a project which requires me to design a system where I can transmit voice over a distance, by inputting an analog voice signal on one end and then recovering the voice which I input on the transmitting end at the receiving end.

The general design (given by my teacher) is here (and I am allowed to modify the design if I wish to):

v3zkuw.jpg


However, I am stuck on the problem of achieving frame synchronisation, which is essential in recovering the voice signal at the decoder (receiver).

Homework Equations

(I will state the components I have in here.)[/B]

TTL I.C.s components:

74 HC 00 NAND gates
74 HC 04 NOT gate
74 HC 32 OR gates
74HC73 Dual J-K Flip-Flops with CLR
74HC74 D-flip-flop
74 HC 164 Parallel-out serial-in shift register
74 HC 165 Parallel-out serial-in shift register
74 HC 191 4-bit counter
74HC297 DPLL

Analog components:

TP3054/TP3057 PCM codec
LM386 Audio amplifier

The Attempt at a Solution



Currently, I have thought of using bit stuffing to achieve frame synchronisation while keeping the probability of the frame marker detector detecting false frames to a minimum via the attempt to eliminate false frame markers. However, in the project, we have to ensure bit synchronisation and hence, the presence of the bit clock hampers our solution, which is to do bit stuffing, since the insertion of a binary digit will extend the bit clock duration and cause bit synchronisation problems between the receiver and transmitter.

Hence, I have modified our solution to the case where, instead of inserting a binary digit, I will change the LSB (least significant bit) of the n-bit codewords, e.g. 01111110 to 01111111, for instance. However, I have 3 questions in mind:

Q1. Is this implementation of my solution possible with the chips I have above?

Q2. How can I tell my chip to change the least significant bit of my n-bit codewords?

Q3. How do I identify the LSB of my n-bit codewords?

Just wondering, if my modified solution of bit stuffing does not work, are there any solutions or resources which I can point to to get ideas for eliminating to a minimum, false frame marker detection by the frame marker detector?

A big thank you to anyone who can help me in my questions above. :D Thanks again!
 
Physics news on Phys.org
  1. Look up SDLC "bit-stuffing" and NRZI coding.
  2. Use "Manchester encoding".
  3. Use Group Coding (4-to-5 bit encoding)
Your problem has been solved in many ways before.
 
Hi Svein.

Thank you for your reply.

In the end, my group used a verifier sort of thing at the receiver side to weed out false frames so the correct frames can be received and processed at the receiver end. :)
 

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