Generate .vcd File for Verilog w/ GTKwave

  • Thread starter Molecular
  • Start date
In summary, the author is trying to generate a .vcd file from his verilog code, but no matter what he does, no .vcd file is generated. He eventually figured out that the .vcd file is generated when the simulation is run, and that he needs to include the keyword "finish" in the code.
  • #1
Molecular
29
0
Hey guys, I've recently started poking around with verilog code and I've made a few programs now and I really want to get a .vcd file or something similar out of my programs so that I can use gtkwave to analyze the program flow.

The thing is, no matter what I do, no .vcd file is generated anywhere. As far as my understanding there are two ways I can do this, by either

a) Adding

initial begin
$dumpfile("file.vcd");
$dumpvars(0);
end

in my code, something which first gave a bunch of errors and suddenly the errors stopped, but no .vcd file was generated, or

b) running the vvp file like so:

$ vvp testbenchfile -vcd

which again, gave me no vcd file to run with gtkwave.

At one point I even found some guys code on the internet and copypasted it to make sure I wasn't doing something wrong, but this didn't give me any vcd file either even though it appearantly did for him. I'm using icarus iverilog, if that makes any difference. Any help would be greatly appreciated, as I have nobody else to ask.
 
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  • #2
Nevermind figured it out, didn't realize the vcp file wouldn't be dumped until I actually run the output from the first simulation.

I feel stupid now ^^
 
  • #3
Here's an example test module that generates the .vcd file. Took we a while to figure out that these:
$dumpfile("test.vcd");
$dumpvars(0,test);
produce the output, and the simulation must be run (see the finished keyword).

module test;

/* Make a reset that pulses once. */
reg reset = 0;
initial begin
$dumpfile("test.vcd");
$dumpvars(0,test);

# 17 reset = 1;
# 11 reset = 0;
# 29 reset = 1;
# 5 reset =0;
# 513 $finish;
end

/* Make a regular pulsing clock. */
reg clk = 0;
always #1 clk = !clk;

wire [7:0] value;
counter c1 (value, clk, reset);

initial
$monitor("At time %t, value = %h (%0d)",
$time, value, value);
endmodule // test
 

Related to Generate .vcd File for Verilog w/ GTKwave

1. What is a .vcd file?

A .vcd file is a Value Change Dump file that is used to store simulation data from a Verilog or VHDL simulation. It contains information about the signals and variables in the simulation, as well as their values at each time step.

2. How do I generate a .vcd file for Verilog?

To generate a .vcd file for Verilog, you will need to use a simulator such as ModelSim or Icarus Verilog. In your Verilog code, you will need to add a command to enable VCD dumping, such as "$dumpfile" and "$dumpvars". Then, when you run your simulation, the .vcd file will be automatically generated.

3. What is GTKwave?

GTKwave is a free and open-source waveform viewer that can be used to view and analyze .vcd files. It allows you to visualize the simulation data in various formats, such as waveforms, tables, and graphs.

4. How do I open a .vcd file in GTKwave?

To open a .vcd file in GTKwave, you can either go to File > Open, or you can drag and drop the file into the GTKwave window. Make sure to select the correct format for your .vcd file, as there are different versions of the VCD format.

5. Can I customize the display in GTKwave?

Yes, GTKwave allows you to customize the display of the simulation data in various ways. You can change the color, style, and size of the waveforms, as well as add labels, markers, and annotations. You can also zoom in and out, and adjust the time scale of the simulation.

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