Help with PLL Circuits | Get Expert Advice

  • Thread starter Thread starter Geeky
  • Start date Start date
  • Tags Tags
    Circuits
Click For Summary

Discussion Overview

The discussion revolves around the design and troubleshooting of Phase-Locked Loop (PLL) circuits, specifically focusing on components such as offset adders, integrators, and rectifiers. Participants share their circuit designs, seek advice on calculations and component functionality, and address issues related to DC offsets in their circuits.

Discussion Character

  • Exploratory
  • Technical explanation
  • Debate/contested

Main Points Raised

  • One participant describes their circuit design, including a summing amplifier and integrator, and expresses confusion about the output voltage calculations.
  • Another participant questions whether power to the op-amps was considered in the calculations.
  • A participant mentions finding a specific IC (XR-2211A) that could be useful but is unclear about how to extract the VCO output from it.
  • One participant reports building their own circuit instead of using the IC and describes its functionality, while also noting a DC offset issue after the full wave rectifier.
  • Another participant challenges the design by asking about the presence of a phase detector and VCO, suggesting that the circuit may not qualify as a PLL.
  • There is a request for clarification on the function of each op-amp block and the nature of the input signal in the circuit.

Areas of Agreement / Disagreement

Participants express differing views on the completeness and correctness of the circuit designs. Some participants agree on the functionality of certain components, while others raise questions about the design's adherence to PLL principles, indicating that multiple competing views remain.

Contextual Notes

There are unresolved questions regarding the calculations for output voltages, the handling of DC offsets, and the overall architecture of the PLL circuit. The discussion reflects a mix of practical circuit design and theoretical considerations.

Who May Find This Useful

Individuals interested in circuit design, particularly those working with PLL circuits, op-amps, and signal processing, may find this discussion valuable.

Geeky
Messages
4
Reaction score
0
Hi guys,

How are you all? I am trying to build to a PLL circuits. As part of the circuit, I will need an offset adder, integrator, rectifier, and another stage of offset adder.

I haven't done circuits for very long time. So please bear with me if I am mistaken.

Appreciate your help.

I have designed the first stage offset adder and integrator.

Please see attached diagrams. Schematic 1 is the circuit for offset adder which basically a summing amplifier, and then the second stage op-amp is the integrator.

The AC source with 1 Vac, is passed through the R3 and R1, R3 will later be a variable resistor when I transfer this to PCB.

From the diagram, I don't understand how the 5V added by V2 becomes 2.5V at the output of U1 (first Op-amp). I tried calculating it out, but could not get the exact point. Please advice.

Then, at the second stage. If you see the frequency response diagram. The 3dB is approximately at 200 kHz. But by using 1/2[tex]\prod[/tex]RC formula, R=R3 and C=C1, which are 1 kohm and 50 pF, respectively, the cutoff should be approximately 3.1 MHz. So I don't really get it. Please advice if I am in the right direction, or the equivalent circuit calculation is wrong.

Please point where I am going wrong. I have also attached the time domain graph. Thank you so much.
 

Attachments

  • Schematic1.jpg
    Schematic1.jpg
    16.9 KB · Views: 530
  • Frequency response.jpg
    Frequency response.jpg
    30.7 KB · Views: 560
  • Time response.jpg
    Time response.jpg
    44.6 KB · Views: 509
Last edited by a moderator:
Engineering news on Phys.org
The numbers don't make any sense to me. Did you forget power to the opamps?
 
Thanks. I fixed it, its the variable resistor. Thanks again.

Between, I have found the XR-2211A that could do the job :

See attached datasheet.

http://www.farnell.com/datasheets/7277.pdf"]http://www.farnell.com/datasheets/7277.pdf"]http://www.farnell.com/datasheets/7277.pdf

The datasheet provides the circuit construction for tone detection, and I need that. But however, it is unclear how could I tap out the VCO output, cause that is what I need, I need the locked VCO output.

Please anyone, advice me, I really don't understand.
 
Geeky said:
The datasheet provides the circuit construction for tone detection, and I need that. But however, it is unclear how could I tap out the VCO output, cause that is what I need, I need the locked VCO output.
I'm not familiar with that IC, but looking at the datasheet I think you could tap the waveform at pin 13 or 14 and use a high-impedance analog buffer/comparator to square it up.
 
I choose not to use the IC. I built my own circuit. Thanks NascentOxygen.

I have built the circuit in practical. Its working fine. But I have a small problem, please see the attached schematic.

So the signal goes through a summing amp, integrator, full wave rectifier and final summing amp. All the sections are working fine. But after full wave rectifier (Op amp U4), there a is a DC offset. I don't want that DC offset. Because I would like to add DC through the final stage of summing amp from 0V to any arbitrary +V. So how can I remove the DC, I don't want any inline capacitor. I am thinking of buffer, will that be the correct move?

Please advice.
 

Attachments

  • Schematic1.jpg
    Schematic1.jpg
    15.8 KB · Views: 531
Geeky said:
I choose not to use the IC. I built my own circuit.
You invented this design yourself, did you? Or what is it based on?

So the signal goes through a summing amp, integrator, full wave rectifier and final summing amp. All the sections are working fine. But after full wave rectifier (Op amp U4), there a is a DC offset. I don't want that DC offset.
That DC component is a consequence of the preceding stages.

I'm not sure this is a PLL. Where is your phase detector? Where is your VCO?
 
Hi NascentOxygen. Yes. I combined bits and pieces from here and there. I have external mixer and VCO. The subsequent mixed baseband signal error signal will go through this circuit.

Thanks!
 
Geeky said:
Hi NascentOxygen. Yes. I combined bits and pieces from here and there. I have external mixer and VCO. The subsequent mixed baseband signal error signal will go through this circuit.

Thanks!
I think you need to explain what each OP-AMP block does here. Where will the error signal connect into this circuit? Is the 100k signal source part of this, and is it sinusoidal or square wave? What function does the fast integrator perform?
 

Similar threads

Replies
2
Views
2K
Replies
9
Views
8K
Replies
26
Views
7K
Replies
6
Views
2K
  • · Replies 3 ·
Replies
3
Views
2K
  • · Replies 6 ·
Replies
6
Views
3K
  • · Replies 5 ·
Replies
5
Views
7K
Replies
12
Views
3K
  • · Replies 8 ·
Replies
8
Views
3K
  • · Replies 21 ·
Replies
21
Views
3K