How Do I Design a Unity Gain Amplifier for a Sample and Hold Circuit?

[sailmike]

I need to design a unity gain amplifier for a sample and hold circuit. I've decided to use the circuit shown in the attachment. Now I know the gain = 0.5(Gm2*R1)[(Gm3*R2)/(1 + Gm3*R2)]. The 2N7000 has a Gm of 0.1, so that gets me the values of R1 and R2. I don't know if these are good values to use. Components Q1, M1, R3, and R4 comprise the bias current source. Obviously, I'm not understanding the theory behind the circuits. I hope someone here can help me understand this better.



Thanks a lot,

Mike

 

[mjhilger]

Several things jump out at me in this circuit for your specified use. First is that M3's current is 500ma, now for a switching function that's ok, but as an amplifier that seems quite high and it will get hot at that drive. M1 & M2 are set in a differential mode where Q1 & M4 provide a constant current source for the differential setup. I think of the differential amp as a seesaw, it is balanced where at quiescent the same current flows through each leg (drain here) and as a signal difference is presented across the gates of M1 & M2 that balance is changed and amplified by the resistors in the drain circuit, in this case R1. This setup provides a very high input impedance and a potentially high gain at R1. R1 sets the impedance output of this setup and normally needs a power output stage to provide a lower impedance output. If you look at a LM741 circuit you will see the similarities of BJT form, but same setup (R1 is replaced by active transistor impedance in the 741). Because you are seeking a unity amp, you have chosen values for R1 & R2 that work in your equation, but are way out of norm for an amp for this function. Total current for this function should be in the 10ma range for the entire circuit.
Then there is the fact that the input is shown as an AC source, this amp will only operate as an amp on signals within the rails (between 0 & V+) and there needs to be head room in there to allow for the bias circuit and range of R1 to stay linear. If you are going to need to use an AC source as input, you will either need to supply your circuit via a -V instead of ground on the lower side or offset your input voltage. Likewise the way the circuit is drawn the gate to M2 is at the bottom of the voltage source so the difference is referenced there. As such the only signal that will be in linear range is positive swings of the AC input. But the M2 gate tied to gnd is problematic just to start. There are several ways to go to achieve what I think you are looking for, but you will need to decide which way and we can help you from there. You could also choose a high gain and employ feedback to stabilize the overall gain back to 1.

 

[sailmike]

I like the seesaw analogy. I forgot to mention that I don't know how to choose the bias current value also. The 2N7000 in this circuit is a custom part and I'm not sure I attached the pin numbers to the right label (gate, drain, source). The data sheet doesn't say which number is which.

This circuit is going to be the sample and hold part of an analog to digital converter.

I see what you mean by only outputting the positive side of the input. I've added a negative supply to the bottom, but this changes the voltage to the base of Q1 to around -4.34 V leading me to believe I need to replace that with a PNP transistor. I've attached the new PSpice analysis.

Using feedback to get the gain back to 1 sounds interesting, but I don't know enough about using feedback. Isn't there a possibility that the output will be a little off from the input with this method?

Thanks,
Mike

 

[mjhilger]

Is this for a one time circuit? Is there a reason you want to use discrete parts? You can accomplish this with one op-amp in a smaller footprint and much lower currents with no external components. A LM741 or similar with your input signal tied to the + input and the output of the op-amp tied back to the - input is a pass through buffer with unity gain and high input impedance. If your input signal is AC with voltage swings above and below gnd, then you will need a V- supply (the swing of your input signal should fall within the supply rails and just a bit more; if you are trying to buffer a 9 v p-p signal then the +5 & -5 should work any input less than that will be fine. You state that this circuit is the sample and hold, but the posted circuit is only capable of buffering. Again, there are chips and circuits that will do the sample and hold with much less hassle then this.
I love the 2N7000 and have used it many times for switching, but true differential setup with minimal offset will require the M1 & M2 transistor be matched, so usually in the same package, 4 in an IC chip so the silicon, temp, and mask are matched. This insures their response Vgs and Gm are equal, at least as close as possible.

 

[sailmike]

The specifications for this project include the use of discrete parts and an input signal of up to 100 kHz. This is going to be an 8-bit converter. My instructor does allow the use of some non-discrete parts, I just have to ask him about them. I've chosen a 12 MHz clock and 1/8th of that is 1.5 MHz, which is what the sample and hold circuit will run at. In one of my classes where this circuit was mentioned, he said that op-amps were too slow. Yeah I only posted the amp part of the sample and hold. The rest of the circuit consists of a high speed switch (DG212), a holding capacitor, and a second amp identical to the first. Both have to have high input impedance and low output impedance. I understand the matching part. I don't have any ideas on part numbers for a matched pair. I figure I should get the amps working good before testing the whole sample and hold circuit together.

Right now I'm looking for a good PNP transistor to use in place of 2N2222.

Thanks,
Mike

 

[sailmike]

Found a 2N3906 and put that in the circuit, but now I'm getting a negative voltage at the gates of M3 and M4. I'm looking this problem wrong. What am I missing? How do I provide a negative voltage to the bottom while also providing the bias current? Is there a better bias current source I could use?

Thanks,
Mike

 

[mjhilger]

Ok, thanks for the clarification. Matched sort of for BJT are 2n3904 & 2n3906. The 2n7000 is fine and will work, I just needed to understand what you are doing with all the circuitry.
The upper and lower voltage rails provide the max swing of the circuit output. Normal op-amps using the single side power supply are expecting the input inside those bounds. So if you are needing to sample true ac where the signal is above and below ground, you need your power to exceed those voltages on both sides also. Normally split supply like +5 & -5. Then the other gate of your differential goes to ground or middle of the rail. The constant current supply for the differential keeps the output of this part linear with varying common mode voltage input. If you are only using this as a buffer, the whole thing, Q1 M4 and such could be replaced by a single resistor or pot to cause the output, R1 to set at 0 (well not necessarily 0, it should be such that your power output stage = 0) for 0 input. You can use the setup you show, but you will need to adjust the values to cause the R1 value to approach 0(same here as above, output of your power stage should be 0) for the 0 input as well. Then the output stage is your issue with the 0.1 resistor. I'm not sure what value cap you plan on using for the "hold", but you can choose a small value with low leakage which will hold your value to the tolerance you need. You will have to work out the numbers. The circuit will work with the right values. V1 minus side should be connected to ground not the bottom rail as shown. Then select a more realistic value for R2, you be the judge, but with other changes 1K should be sufficient. But you should look at your switch and the hold cap value that will provide small enough sag and the output impedance from your buffer circuit that will provide fast enough charge time for largest values sampled.
This seems like a good learning exercise, but advanced. Look at your values again and adjust them for currents in the microamps or small milliamps. Search the web for other circuit values and specs that will help you determine the currents and values for your hold cap and I think you will have a good starting position to work back into your buffer circuit to find better values.

 

[AlephZero]

Even with discrete parts, why do you need all this complexity? Wouldn't a simple emitter follower (with a Darlington transistor if you want very high input impedance) do the job? Clock speeds of a few MHz and 8 bit accuracy are not too demanding.

 

[sailmike]

Well one problem is, I don't know what a typical analog input voltage looks like. Do they typically go below ground? What's the voltage swing?

Don't MOSFET's have higher input impedance and lower quiescent current than BJT's?

Thanks,
Mike

 

[mjhilger]

We do not know your design parameters. That should be specified in your statement of work, or lab problem. AlephZero provides a good simple alternative to your problem. I love using differential pairs, but it does seem overly complex for your stated need. Its all your choice. I highly suggest you look at some of the microcontroller data sheets for their A/D inputs and look at their equivalent input sample and hold. Specifically look at their input impedance and voltage range. Any of the Microchip PIC parts should provide some useful information.

 

[sailmike]

That's a great tip! The attachment shows an example and it looks like the input voltage is 0 to Vref. I'm not sure what the other two Vin's mean. The design parameters didn't include the input voltage range, just the maximum frequency, which is 100 kHz.

The emitter-follower I attached is good enough for my purposes? R1 and R2 will have to be in the 100k ohm or higher range to get the high impedance input?

Thanks,
Mike

 

[mjhilger]

Your attached amp is good, but what if your signal is DC? The caps that provide isolation from the DC bias differences, also prevent working for DC inputs. You can easily configure that circuit without caps and a couple other components (and maybe a negative voltage source as before or different way to inject your input voltage) to provide the buffering you seek. Its good you are opening your options and considering other choices. You are very close to a good solution.

 

[sailmike]

I'm always open to other ideas.

I've got the basic emitter-follower down. The output is offset by about -600.8mV. There is not supposed to be any offset, but I'm not seeing how to get rid of it.

Thanks,
Mike

 

[mjhilger]

What component has a consistent drop of about 600mv? If such a component exists, can you place it in a location to offset the output voltage back closer to 0? Are there any constraints of the actual A/D that still need consideration because of the AC negative swing? <- This one is one I really don't know about.

You will need to determine what voltage swing is allowed and you may have to shift or reduce the input buffer gain (or both) to match the constraints of the A/D being fed.

 

[sailmike]

Ok, there is a voltage drop of 4.4V across R3 leaving -600mV at the emitter. The negative supply confuses me. I haven't worked with any circuits like this involving a negative supply, just ground.

I have 1V for the base voltage minus the roughly 0.7V drop across Vbe. I know I need something else to pull the voltage back to zero, but I'm not seeing how to do it.

I'm building a SAR ADC. Most of the circuit is done. All that's left is the sample and hold and comparator.

Thanks,
Mike

 

[mjhilger]

How about a diode with the cathode tied to the collector, you will have to forward bias the diode, but the signal on the anode side will be about 0.6 above the collector voltage. You will just need to determine the current necessary for your purpose.

 

[sailmike]

I think I understand what you mean. I want to cancel out the -600.8mV by adding +600.8mV to that? I don't see how to hook up the other end of the diode to achieve that. I know you gave me a big clue. I'm also noticing that there's zero volts at the base of Q1.

Thanks,
Mike

 

[mjhilger]

How do you forward bias a diode?

The 0 volts at the base is the result of V3 having a V offset of 0 volts. If you disconnect V3, it will fall more in line with the voltage divider bias point. But because it is an emitter follower you don't really care, because it should follow V3 at whatever instantaneous voltage is presented.

You're really close, you can figure this out.

mitch

 

[AlephZero]

You don't have to shift the amplifier output by 0.6V. You could shift the zero reference of the ADC by 0.6V to compensate.

 

[sailmike]

Oh I know to use resistors to bias the diode. I just don't know where to connect the other end. I tried the connection shown in the attachment, which I know is wrong, since I'm getting the wrong output. I just realized that the diode is not forward biased in this circuit. Adding an Rc resistor changes the output voltage at Ve.

Thanks,
Mike

 

[mjhilger]

Mike, I owe you an apology. I said collector and I meant emitter. The cathode attached at the emitter and a resistor from the anode to +5 top rail will forward bias the diode and your anode will be approximately 0.6 v above the emitter. But Alephzero also has a good suggestion of using the offset on the A/D reference circuit.

Welcome to design engineering! You always have choices and I have struggled at times with two good solutions trying to determine which is the best. Ultimately you must decide a direction and implement.

Again, I'm really sorry for stating the wrong leg.
mitch

 

[sailmike]

Oh no problem, we all make mistakes. We wouldn't learn anything if we didn't.

That makes better sense. Right now it's cutoff around zero. The negative portion of the signal is cutoff.

Thanks,
Mike

 

[sailmike]

Alright, here's what the circuit looks like now. The results are wrong though. I can't seem to get a 0.6V difference between the cathode and anode of the diode, perhaps because of the specific diode I'm using in the simulation. Also attached is the output graph. The negative side is partly clipped.

If I was to offset the reference voltage, how would I do that? I'm allowed to use a DAC chip and that has a Vref input. Can I use that input to offset the reference voltage? If I go that route, it may be a good idea to use a potentiometer in place of a resistor so I can adjust the reference voltage to match the offset more precisely.

Thanks,
Mike