How can I improve the linearity of my VCO circuit design?

[crixus]

I recently designed a circuit of VCO and obtained a plot for frequency v/s Vc(control voltage).

The graph was pretty much linear for a certain range of Vc but tends to become non linear when Vc is further increased or decreased.

How do I explain the non linearity...??

The schematic of VCO is attached...

Thanks in advance :)

 

[dlgoff]

Am I missing something? Here's how the op-amp VCOs I've played with look:

https://docs.google.com/viewer?pid=bl&srcid=ADGEESimoJCAMx6IQHLpp_FE5UgepkMJGWiuMI0CYYlUlayq9TYw-n1CtB5YQ7y2qtGhWGkS1ANLGVDaCoiTcwWyI9P2XxL2VqQHRanNpH9GUJhagYCSVwK5F2PDqDo-sUTAWroVN0TX&q=cache%3Aw5Po-sybfrYJ%3Awww.national.com%2Fds%2FLM%2FLM124.pdf%20lm324%20vco%20schematic&docid=83316e81b78e6fa9f33bc9a05287bd31&a=bi&pagenumber=13&w=800

National datasheet for the LM124/LM224/LM324 Quad op-amp

 

[crixus]

The VCO is not completely op amp based... Let me make it easy...

The VCO here has three parts
1) A transistor switch - Controls charging and discharging of capacitor
2) A Schmitt trigger - Which Controls the transistor switch.
3) The current sources I1 and I2

Although i am clear about the working of this circuit but cannot figure out the cause for non linearity.. :(

 

[dlgoff]

Am I missing something? Here's how the op-amp VCOs I've played with look:

...

National datasheet for the LM124/LM224/LM324 Quad op-amp

This is the schematic I was trying to display from Nationals datasheet.

http://old.nabble.com/attachment/27816429/0/Circuit%20VCO%20LM324%20600.gif

 

[crixus]

Whatever the schematic , the fact is VCO shows non linearity in its frequency vs Vc(control voltage) characterstic. Can u explain that ?

 

[dlgoff]

Whatever the schematic , the fact is VCO shows non linearity in its frequency vs Vc(control voltage) characterstic. Can u explain that ?

Okay. For operational amplifiers: Saturation, Slewing, and Non-linearity from input to output.

Operational Amplifier Non-linear imperfections

 

[NascentOxygen]

I recently designed a circuit of VCO

You have some very elaborate circuits there. How do you connect them up to make the VCO? What frequency range are you getting?

 

[crixus]

First look at the diagram on the extreme left...

There are two current sources whose elaborate ckt is given in he middle diagram.

the current source I1 charges the capacitor until it reaches Vh which changes the output of the schmitt trigger(right) and connects I2 to capacitor as well.Now if I2>I1 then capacitor will discharge which makes capacitor voltage to fall to Vl which makes the schmitt trigger to change its state again.
Thus we get a triangular wave with charging and discharging times determined by I1 and I2-I1.
If you look closely it is mentioned in the diagram which parts are connected in what fashion.

The frequency range I got was 0.5 khz to 3 khz using Vc between 10V to -10V

 

[crixus]

Here I have highlighted what is necessary for better understanding... :)

 

[jim hardy]

It is not clear what Vh and Vl should be,
because no resistor values are shown for R4 and R5.
Still, it looks like they should be fairly symmetric about zero

But it looks to me like Vl could not be much more negative than 0.6 volts with T5's base at circuit common..
What's AGND? Is it different from GND?

When T4 is ON, T5's E-B junction sees 10 to 12 volts reverse. I don't know what is that transistor's V_ebr limit but if i recall, 6 volts is typical for general purpose NPNs.

i suspect your trouble is around T5.

old jim

 

[NascentOxygen]

The frequency range I got was 0.5 khz to 3 khz using Vc between 10V to -10V

That is a disappointingly narrow range, 1:6. Were you happy with it? Was this just a circuit to investigate as an exercise, or do you have a practical use for a VCO? With a different/better circuit you should be able to get 1:200 range at least, with good linearity, if needed.

 

[NascentOxygen]

It is not clear what Vh and Vl should be,
because no resistor values are shown for R4 and R5.

No component values are shown for any of the circuits--not the Schmitt trigger nor the current sources. Perhaps OP should tell us what values he used, and how he worked them out? Also the capacitor value.

When T4 is ON, T5's E-B junction sees 10 to 12 volts reverse. I don't know what is that transistor's Vebr limit but if i recall, 6 volts is typical for general purpose NPNs.

Data sheet for BC547B says 6 volts. So it seems you may have found a flaw with the design.

i suspect your trouble is around T5.

Trouble? I didn't understand OP to be saying there was something wrong with its operation, just how to account for its characteristic (which I admit is disappointing, for something so elaborate). We'd really need to see T5's Vbe waveform to decide whether it is breaking down.

You have highlighted something that seems to be wrong with the design. No saying that this particular transistor is breaking down, though.

 

[jim hardy]

yes , any individual transistor might well be tougher than guaranteed on datasheet.

Maybe he'll say what is Vl.
In my mind's eye, when i think of T5 as just two diodes,
his C-B becomes forward biased if capacitor voltage ever tries to go below negative 0.6 .
So current out of that node is no longer just I2 and i'd expect its F/V slope to change when that happens.

but I'm no expert.

 

[NascentOxygen]

but I'm no expert.

You're doing well.

Possibly nothing more is needed to knock the circuit into decent shape than a change in the supply voltages. This would smarten up that op-amp Schmitt trigger, and should move the operating voltages within the safe range of the specified transistors.

Though looks like OP has lost interest, or the assignment deadline has passed...

 

[fbs7]

This circuit looks very much like the internals of the NE 566 chip:

The basic idea is a voltage-controlled current source that charges a capacitor at constant current and is connected to a schmitt trigger, which in turn connects to a switch that discharges the capacitor at constant current.

I guess the OP diagram missed the proper placing of the transistor switch?

 

[fbs7]

After looking the OP's circuit a bit more, I don't think it will work properly, because his current mirrors will not be linear. This is my take on a VCO on the OP's configuration. The idea is pretty simple: your Vinput (the 10Khz signal) defines a current on T4 (Io = (Vin-0.6)/1K), which is mirrored on T5, T6 and T7; T3 then mirrors the current at T5, and T2 mirrors T3. The final effect is that the current on all transistors is the same, so if T1 is cut-off then the capacitor loads at rate Io; when T1 flips to conducting, T6 and T7 will drain Io each so both will drain 2xIo, and the capacitor will discharge at Io - 2xIo = -Io. The VCO cycle is always 50%.

I guess this is more or less what the OP intended.