Latches and flip flops - how is stable state defined?

  • Thread starter Thread starter Same-same
  • Start date Start date
  • Tags Tags
    Stable State
Join the discussion
Ask a follow-up here, or get your own question answered by working scientists, mathematicians and engineers — people, not an autocomplete.
Real named experts · corrections over time · the nuance an AI answer skips
3 replies · 9K views
Same-same
Messages
27
Reaction score
0
Latches and flip flops - how is "stable state" defined?

My textbook and professor both make numerous references to "stable state" of a latch of flip-flop, but never actually define it.
It's not intuitive. For instance, if the present output Q is 0, and we input S=1 and R =0, the circuit's next state, Q+ , is 1, and this is a stable configuration, but the textbook says this is not a stable state.
So what does "stable state" actually mean in this context?
 
Engineering news on Phys.org
I'm not aware of how the application of a steady state 1-0 or 0-1 input to an S-R latch (using nor2 or nand2 gates) can result in an unstable state except during the period of transition. But I expect the textbook is correct and I am missing some information. Perhaps it is referring to the transient state during which the output is 1-1 (nand) or 0-0 (nor) due to propagation delays.
 
Same-same said:
My textbook and professor both make numerous references to "stable state" of a latch of flip-flop, but never actually define it.
It's not intuitive. For instance, if the present output Q is 0, and we input S=1 and R =0, the circuit's next state, Q+ , is 1, and this is a stable configuration, but the textbook says this is not a stable state.
So what does "stable state" actually mean in this context?
I'd need you to sketch the gate arrangement to be sure, but I think you will find that a state which exists only while it is forced by the continued presence of a peculiar input is considered not a stable state. A stable memory state is one that will be maintained even when the inputs revert to their inactive/neutral level (the STORAGE state).

I can't comment on any distinction re a "stable configuration" vs "stable state"
 
The word 'stability' can refer to several different things. This can lead to confusion.
Stability, in this context usually refers to a situation in which, when a small perturbation is introduced, a system will return to its original state. In electronics, you can get stability with positive feedback (as with a simple 'bistable' circuit - Google gives dozens of hits). Stability in this sense requires some non-linearity. Once the bistable circuit is in one state (i.e. the output is hi or lo) then the input signal needs to cross a certain threshold value for the state to change - then the output state will swing to the other stable state. So the input output characteristic will be a 'step'.
A Schmitt trigger is another circuit which has 'hysteresis' which is a decision making circuit that cuts out the effect of low level noise on a signal. Once the input reaches a certain level, the Schmitt 'decides' it's high enough in level so it 'flips', the input signal then needs to go to a significantly low level before it decides to flip back.