Latches and flip flops - how is "stable state" defined? My textbook and professor both make numerous references to "stable state" of a latch of flip-flop, but never actually define it. It's not intuitive. For instance, if the present output Q is 0, and we input S=1 and R =0, the circuit's next state, Q+ , is 1, and this is a stable configuration, but the textbook says this is not a stable state. So what does "stable state" actually mean in this context?