How to determine minimum amount of AND and OR gates in PLA?

[Peter Alexander]

Homework Statement

Realization of given three functions
$$
\begin{array}{c} f_{1}=x_{1}\bar{x}_{2}\bar{x}_{3}+x_{2}x_{3}\bar{x}_{4}\\ f_{2}=\bar{x}_{3}x_{4}+x_{1}\bar{x}_{2}\bar{x}_{3}\\ f_{3}=x_{2}x_{3}\bar{x}_{4}+\bar{x}_{3}x_{4} \end{array}
$$
using the PLA.

Homework Equations

I don't know what to write here. Probably that according to Wikipedia, PLA should have $2^n$ AND Gates for $n$ input variables and for $m$ outputs from PLA, there should be ## OR Gates

The Attempt at a Solution

The thing is that I'm completely stuck on this problem and I don't even know how to begin. I do have a decent background in combinational logic circuits, but not in the PLA as I don't understand it at all. The solution, however, is known to be 3 AND and 3 OR gates.

Can someone please give me some information on how to begin solving this task? I don't think I need the full procedure, only some advice on where to begin or where to look.

Any sort of helpful information is welcomed.

 

[jaus tail]

Are you sure this is the right question? You'll also need some NOT / NOR / NAND / XOR / XNOR gates. You need this to get the complementary terms. i.e x'

 

[Peter Alexander]

Yes, double checked it. The thing is, it did take me awhile, but I think I understand how PLA works. It's composed of AND and OR plane. Input variables, in this particular case, are brought to the AND gates. Connections must be programmed. From AND gates connections lead to OR gates and those connections need to be programmed as well.

I don't know, however, how to produce the minimum amount of AND and OR gates.

Edit: the construction of PLA I'm mentioning comes DIRECTLY from how professor explained it to us. He never told us how to minimize the design, though.

 

[berkeman]

Does this figure help? It kind of depends on the PLA, but this shows a typical architecture. Does it match the PLAs that you have been discussing in class?

https://courses.cs.washington.edu/courses/cse370/99sp/lectures/03-CombImpl/img048.gif

 

[donpacino]

I don't know, however, how to produce the minimum amount of AND and OR gates.

If you have a decent background in digital logic you should know these things. see the website in the line below for tools you can use.
http://district.bluegrass.kctcs.edu/kevin.dunn/files/Simplification/4_Simplification_print.html

That being said, look into kmaps. By writing the solutions over 1 kmap, you may be able to find different ways to reduce across the three functions
3.

Also for this problem do you have access to both the input and the inversion of the input? (you should if its a good PLA). This will make it trivial to find the solution

 

[Peter Alexander]

I would like to thank both of you (sorry for the delayed response). I actually figured out how things work, and the links you provided, along with the replies, really helped a lot.

Thank you so much!