How to Draw Logic Gate Graphs for NOR and XOR Gates

Click For Summary

Discussion Overview

The discussion revolves around drawing logic gate graphs for NOR and XOR gates as part of a homework assignment. Participants share their attempts, corrections, and insights related to the graphical representation of these logic gates.

Discussion Character

  • Homework-related
  • Technical explanation
  • Debate/contested

Main Points Raised

  • Initial homework statement includes drawing outputs for NOR and XOR gates based on given inputs.
  • Some participants provide feedback on the correctness of the graphs, with one noting a specific mistake related to the XOR representation.
  • There is confusion expressed about how to represent XOR on a single graph, with one participant suggesting they have figured it out after some thought.
  • Another participant suggests simplifying the approach by using fewer graphs and focusing on the exclusive-OR rule for drawing outputs.
  • Participants discuss the value of thoroughness in problem-solving, with some advocating for a rigorous approach while acknowledging the potential for mistakes with more complex steps.
  • One participant expresses satisfaction with their revised graph, indicating it now looks correct.
  • Additional practice is encouraged, with a participant sharing new graphs for OR and AND gates and seeking feedback on their accuracy.

Areas of Agreement / Disagreement

Participants express differing views on the complexity of the task and the best approach to drawing the graphs. Some agree on the value of thoroughness, while others emphasize simplicity. The discussion includes multiple corrections and refinements, indicating that no consensus has been reached on the optimal method for drawing the graphs.

Contextual Notes

Participants reference specific mistakes and corrections without resolving all issues, indicating ongoing uncertainty in the graphical representations. The discussion highlights the importance of understanding the logic behind the gates while grappling with the graphical output.

Femme_physics
Gold Member
Messages
2,548
Reaction score
1

Homework Statement



Graphs A and B are entries to a NOR gate with 2 inputs. Draw the output C.

Graphs X and are entries to a XOR gate. Draw the output Z.

Homework Equations



abxy.jpg



The Attempt at a Solution


NOR.jpg



XOR.jpg
 
Physics news on Phys.org
Looks good.
 
I'm afraid you've slipped at ##\overline{x} \cdot y##.

Tip: XOR means "either the one, or the other (but not both)".
 
I like Serena said:
I'm afraid you've slipped at ##\overline{x} \cdot y##.

Tip: XOR means "either the one, or the other (but not both)".

I'm confused...if XOR mean either this or that, how can u draw it on a single graph?

EDIT: nevermind, I think I figured it out
 
Last edited:
You are making heavy work of this, Femme_physics. Would you like to start again?

All you need are 3 graphs: x and y, and a blank one for your answer. https://www.physicsforums.com/images/icons/icon3.gif

Now graph the answer following this EXCLUSIVE-OR rule: where x differs from y, draw
logic level 1. (And if x equals y, draw level 0.)

That's all there is to it. Too easy! :smile:

I'm not sure why your output trails off to the right at logic 1, where x and y are both at 0 https://www.physicsforums.com/images/icons/icon5.gif
 
Last edited by a moderator:
I'm not sure why your output trails off to the right at logic 1, where x and y are both at 0

Oops, you're right, but I think this is my only mistake right?

As far as "heavy work" -- well, I think it has an added value, being more thorough allows you to see the whole picture and revise the issue better.
 
Femme_physics said:
Oops, you're right, but I think this is my only mistake right?
You have made another careless mistake, which will reveal itself.
As far as "heavy work" -- well, I think it has an added value, being more thorough allows you to see the whole picture and revise the issue better.
Exactly right, there is much to be gained by doing it the rigorous way, if only to confirm that the formula jives with the common sense approach. Unfortunately, the more steps you go through, the greater the opportunity to make mistakes. If this were an exam question, I'm sure the time allocation would be for the simple route. It is good to know how to do the task both ways.

If you solve a problem two ways, agreement of answers usually confirms you as being correct. Disagreement can often highlight the error.
 
You have made another careless mistake, which will reveal itself.

Oh yes, I forgot to include that little block in the middle. Thank you :smile:

Exactly right, there is much to be gained by doing it the rigorous way, if only to confirm that the formula jives with the common sense approach. Unfortunately, the more steps you go through, the greater the opportunity to make mistakes. If this were an exam question, I'm sure the time allocation would be for the simple route. It is good to know how to do the task both ways.

If you solve a problem two ways, agreement of answers usually confirms you as being correct. Disagreement can often highlight the error.

Completely agree :approve:
 
  • #10
Congratulations on your 2000th post to physicsforums, Femme_physics!
SUDsB.gif
 
  • #11
Last edited by a moderator:
  • #12
Finally looks right. :wink:
 
  • #13
Thanks :)
 
  • #14
Last edited by a moderator:
  • #15
Femme_physics said:
Trying to get more practice.
Good idea. Don't forget exclusive-OR, too. :cool:
Here A and B are Or Gates, with C being the outcome

X and Y are AND Gates, with Z being the outcome

I drew the graphs of the outcome.

Looks good?
yes​
 
Last edited by a moderator:
  • #16
Thanks NascentOx :)
 

Similar threads

Proving XOR Gate Universality: Elementary Operations & Logical Manipulation
  • · Replies 10 ·
Replies
10
Views
3K
Engineering Combinational Logic Circuits using Logic Gates
  • · Replies 1 ·
Replies
1
Views
2K
Designing an XOR Gate from NOR Gates: Truth Tables and Boolean Algebra
  • · Replies 4 ·
Replies
4
Views
6K
Engineering Circuit Realization of XOR function with Three inputs
  • · Replies 4 ·
Replies
4
Views
5K
Engineering XOR Gate Circuits: Draw Z with Lowest # of 2 Input Gates
  • · Replies 12 ·
Replies
12
Views
3K
Designing a NAND Gate Logic Circuit
  • · Replies 2 ·
Replies
2
Views
2K
Implementing a boolean function using NOR gates
  • · Replies 1 ·
Replies
1
Views
3K
Engineering Write the Boolean expression of a given logic circuit
  • · Replies 2 ·
Replies
2
Views
3K
Designing a 2-bit Comparator with NOR gates
  • · Replies 7 ·
Replies
7
Views
8K
How Can You Simplify Boolean Expressions Using Only NOR Gates?
  • · Replies 2 ·
Replies
2
Views
2K