How to Introduce Delays Between Commands in Verilog?

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To introduce delays between commands in Verilog, a counter must be defined that utilizes the clock signal. The logic for resetting and starting the counter, as well as detecting when it reaches the terminal count, is essential. This setup allows for precise timing control, enabling a 2-second delay between each command execution. Implementing this counter logic will facilitate the desired sequential command execution with specified delays. Understanding these concepts is crucial for effective Verilog programming.
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Ok, I am extremely new at verilog and have a very basic question. forgive how elementary this is. I have about 5 commands between a "begin --- -- -- -- end" scenario, but what I need is for it to lag about 2 seconds between each command ie, execute a, wait 2 seconds, execute b, wait 2 seconds, execute c.. and so on. I am just wondering the easiest way to do this. Any general pointing in the right direction would be appreciated. Thanks!
 
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BEEFCOPTER said:
Ok, I am extremely new at verilog and have a very basic question. forgive how elementary this is. I have about 5 commands between a "begin --- -- -- -- end" scenario, but what I need is for it to lag about 2 seconds between each command ie, execute a, wait 2 seconds, execute b, wait 2 seconds, execute c.. and so on. I am just wondering the easiest way to do this. Any general pointing in the right direction would be appreciated. Thanks!

You need to define a counter with clock, and define the logic for the reset/start and terminal count detection.
 
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