IC Physical Design Software Inquiry

[Apogee]

For a traditional circuit simulator, like the free and open source versions of SPICE (i.e. ngspice), it seems to me that they can technically all simulate the same kinds of circuits. Assuming you had a portable SPICE model (either written in SPICE or compiled with ADMS), you could simulate the same circuit in ngspice that you would in a proprietary tool like HSpice.

So, my question is this... We have open source tools for physical digital/analog IC design (layout editors, circuit simulators, etc.). Why is it that anyone would pay $100k+ for a proprietary simulator when they could "theoretically" simulate the same behavior in an open source tool? Is it that the proprietary simulator performs better, or that you can't actually simulate the SAME behavior in an open source tool?

 

[phyzguy]

The proprietary tools typically have features that the open source tools don't. For example, simulating today's very small MOSFETs involves device physics that isn't present in older SPICE models. So you can't get the necessary accuracy unless you have a version of SPICE that incorporates the new physics. Also, I think the proprietary tools integrate more of the tools together better. You can't simulate a chip with a billion transistors using SPICE - it simply requires too much computing power. So large chips are simulated with "mixed-mode" simulators, where part of the chip is simulated at the logic or timing model level, and part at the more detailed SPICE level. Doing this requires that all of the different simulators play together and each understands the output of the other. I don't think the open source tools have this level of integration.

 

[berkeman]

For a traditional circuit simulator, like the free and open source versions of SPICE (i.e. ngspice), it seems to me that they can technically all simulate the same kinds of circuits. Assuming you had a portable SPICE model (either written in SPICE or compiled with ADMS), you could simulate the same circuit in ngspice that you would in a proprietary tool like HSpice.

So, my question is this... We have open source tools for physical digital/analog IC design (layout editors, circuit simulators, etc.). Why is it that anyone would pay $100k+ for a proprietary simulator when they could "theoretically" simulate the same behavior in an open source tool? Is it that the proprietary simulator performs better, or that you can't actually simulate the SAME behavior in an open source tool?

What fab(s) are you targeting for your ASIC design? What geometry is your goal?

Different foundries will have their own component libraries that you need to use in your simulations, and I doubt that foundries that are fabricating at the smaller current geometries would make their libraries available for free to open source simulator programs. I know that at my work, we have paid substantial IP fees to have access to the foundry libraries that we have used in our last few ICs that we have designed and fabricated...

Typically (in my experience lately), foundries will not accept your design for fabrication until you have shown adequate design margins using their component libraries.

 

[Apogee]

For example, simulating today's very small MOSFETs involves device physics that isn't present in older SPICE models. So you can't get the necessary accuracy unless you have a version of SPICE that incorporates the new physics.

So, if I understand correctly, the SPICE models (which I presume are provided by the foundries, but correct me if I'm wrong) incorporate the newer device physics present in cutting edge processes. However, the tools themselves also have features that allow you to simulate things that you just can't do with an open source simulator. Is this because the proprietary vendors are able to collaborate with foundries and thus develop these features with that information? Or is that irrelevant/nonexistent?

 

[Apogee]

What fab(s) are you targeting for your ASIC design? What geometry is your goal?

Different foundries will have their own component libraries that you need to use in your simulations, and I doubt that foundries that are fabricating at the smaller current geometries would make their libraries available for free to open source simulator programs. I know that at my work, we have paid substantial IP fees to have access to the foundry libraries that we have used in our last few ICs that we have designed and fabricated...

Typically (in my experience lately), foundries will not accept your design for fabrication until you have shown adequate design margins using their component libraries.

Nothing specific. This was more a question out of intellectual curiosity. :)

So, the foundry models won't run on open source tools?

 

[berkeman]

So, the foundry models won't run on open source tools?

They may, but you need to pay lots of money to use the models from the foundry, so that kind of is in conflict with your wish to use open source tools to save money, no?

EDIT/ADD -- Also, often the foundry needs to see the results of your simulations before they allow you to tape out the chip and order masks. They want to know that your ASIC will work with high yield before they commit resources to fabricating it. That is usually part of the contract you sign with them, in my experience. So they may be less likely to accept the results of anything other than the industry standard HSPICE, for example. I've seen that before here at work, where we needed to keep our HSPICE license current, in order to satisfy the foundry requirements, even though we did the majority of our other circuit simulations with Analog Workbench on SUN workstations, and then more recently using MicroCAP SPICE on Windows PCs.

 

[Apogee]

They may, but you need to pay lots of money to use the models from the foundry, so that kind of is in conflict with your wish to use open source tools to save money, no?

EDIT/ADD -- Also, often the foundry needs to see the results of your simulations before they allow you to tape out the chip and order masks. They want to know that your ASIC will work with high yield before they commit resources to fabricating it. That is usually part of the contract you sign with them, in my experience. So they may be less likely to accept the results of anything other than the industry standard HSPICE, for example. I've seen that before here at work, where we needed to keep our HSPICE license current, in order to satisfy the foundry requirements, even though we did the majority of our other circuit simulations with Analog Workbench on SUN workstations, and then more recently using MicroCAP SPICE on Windows PCs.

Would you still have to pay for the SPICE models even if you purchased a proprietary simulator, or would they come packaged with them?

Okay, so even if you could get an open source simulator to work as well as HSPICE or other tools, you'd need to convince the foundry as well. Is this correct?

 

[berkeman]

Okay, so even if you could get an open source simulator to work as well as HSPICE or other tools, you'd need to convince the foundry as well. Is this correct?

That is my experience. It was expensive for us to maintain the HSPICE license and support, but we had no choice at the time. I think our foundry was TSMC at the time, but we have also used other foundries.

 

[berkeman]

Would you still have to pay for the SPICE models even if you purchased a proprietary simulator, or would they come packaged with them?

Those are two different things. The simulation software (like HSPICE) is separate from the model files. You license one from the SPICE vendor, and you license the model files from the foundry or their representatives.

 

[analogdesign]

There is also a matter of performance. Industrial SPICE-like simulators (such as Spectre, Eldo, and HSPICE) are very good at re-partitioning matrices on the fly and are able to get 1000X or more performance improvement compared to a free tool. They also have much better ability to simulate large netlists. While a circuit you input into LT Spice or something may have a few hundreds of nodes I've simulated circuits (post-parasitic extraction) with 100s of millions of nodes.

Beyond scale, these expensive simulators have a lot of advanced features such as the ability to simulate different regions of a netlist at different levels of accuracy. This can be very helpful if you have a calibration loop, for instance. You can simulate the digital at low accuracy but keep full accuracy on your sensitive analog signal path.

Additionally, commercial tools have the ability to co-simulate with Verilog (and some, such as Questa-ADMS can actually co-simulate SPICE-compatible netlists along with Verilog using a single kernel). In industry reliable co-simulation is a must.

Lastly, the real killer-app is verification. There isn't anything free that can hold a candle to something like Calibre or Assura. Calibre is the gold-standard so even if you use another verification tool your layout will be checked using Calibre by the foundry (at least the foundries I use).

That isn't to say you can't make a chip without these tools. For simple stuff, you can use something like Tanner or even Magic (or Ledit or Electric) for Layout. Then you can simulate with LT Spice as long as you get reasonable models from the foundry. For anything advanced, you're probably stuck with Cadence at least for the front end. They are the Microsoft of the EDA world.

For digital stuff it can be a lot different. The tools are still really expensive but you can get away without using SPICE these days on a purely digital design.

 

[berkeman]

Thanks @analogdesign -- amazing knowledge and experience. .

 

[Apogee]

Yes, thank you @analogdesign ! :D