Implementing Logic Using Conventional CMOS Logic

[STEMucator]

Homework Statement

This question has several parts, and I'm confused about some of them.

Consider $Z = \overline{(A + B \bar{C})D + E \bar{F}}$. Assume primary and inverted inputs are available.

A) Implement the function in conventional CMOS logic style such that only 4 transistors are connected to the output node, and the PMOS and NMOS transistors with input "A" are attached to $V_{DD}$ and ground (by their source), respectively. Assume all PMOS have $W/L = 15$ and all NMOS have $W/L = 6$. Place a $50 fF$ load capacitance at the output.

B) and C) I had no problem with.

D) Calculate the worst-case rising and falling propagation delays. Only consider the load capacitance and ignore the internal capacitances.

E) No problem.

F) Calculate the best-case rising and falling propagation delays. Only consider the load capacitance and ignore the internal capacitances.

G) Design the same circuit for equal rising and falling delays of $100 ps$. Provide two sizing solutions and indicate $W/L$ of the transistors on the circuit. Identify the better solution with a reason.

Homework Equations

$D_r = \frac{C_L V_{DD}}{2 I_P}$
$D_f = \frac{C_L V_{DD}}{2 I_N}$

The Attempt at a Solution

Here is my work so far:

I want to know if my answer to part A) looks okay.

I know the answers to B) and C) are correct.

D) To find the worst case delay, I have to consider the longest critical path or something along those lines. I am unsure how to do this question.

E) This question is doable if I can solve D) and so I won't need to talk about it.

F) The best case delay means all the paths are active at the same time. I am still unsure.

G) I will get to this.

If part A) looks okay, I need some help with part D).

Thank you.

 

[STEMucator]

I did some research and I found these important facts:

- Designing a conventional CMOS circuit means a PMOS pull-up network and an NMOS pull-down network must be constructed.
- The PMOS pull-up network and NMOS pull-down network must be complements of each other.
- The PMOS network must have the AND terms in parallel and the OR terms in series.
- The NMOS network must have the AND terms in series and the OR terms in parallel.

Using these important facts, I designed this much simpler looking circuit, which I believe is what I am looking for:

I hope that circuit looks okay now. I used both the primary and inverted inputs, and I believe I met the criteria. P.S: I didn't label the sizes.
Now part D) makes more sense to me.

For $D_{rising}$, I need to consider the longest path through the PMOS transistors (there are four such paths at a first glance). I should compute $W_P$ from the minimum of the four widths along each path (using the result $W_P = 1.35 \mu m$ from part B)), and then use that to calculate $I_P$. From there I can calculate $D_r$.

Similarly, for $D_{falling}$, I need to consider the longest path through the NMOS transistors (there are two such paths at a first glance). I should compute $W_N$ from the minimum of the two widths along each path (using $W_N = 0.54 \mu m$), and then use that to calculate $I_N$. From there I can calculate $D_f$.

Part E) is quick.

For part F) I need to consider the best case delays, so I consider the circuit when all the paths are conducting. Then I should follow the same process as in part D), but there are only two widths to consider instead of six. I should use $W_P = 1.35 \mu m$ and $W_N = 0.54 \mu m$.

For part G) I should use an equivalent inverter from the start and use the given delays to compute the respective currents. Then I should take those currents and compute $W_P$ and $W_N$. Then I need to design the same circuit from A) using these new widths, but I need to make sure I design it so the PMOS network transistors can reduce to the equivalent inverter PMOS. Similarly, I need to make sure the NMOS network transistors can reduce to the equivalent inverter NMOS.

If that all sounds reasonable, I can relax.