Linear Feedback Shift register of size 2^7

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SUMMARY

The discussion focuses on the implementation and understanding of Linear Feedback Shift Registers (LFSRs) of size 2^7, specifically using polynomial representations such as x^7 + x + 1 and x^7 + x^3 + x^2 + x + 1. It highlights the importance of avoiding prohibited states, such as all ones or all zeros, which can cause the register to lock. Additionally, the implications of using only 7 bits from an 8 or 9 bit maximal length LFSR are questioned, particularly regarding state generation.

PREREQUISITES
  • Understanding of Linear Feedback Shift Registers (LFSRs)
  • Familiarity with polynomial representations in binary systems
  • Knowledge of state initialization techniques for shift registers
  • Basic concepts of maximal length sequences in digital circuits
NEXT STEPS
  • Research the initialization techniques for Shift Feedback Shift Registers (SFSRs)
  • Study the implications of polynomial feedback in LFSR design
  • Learn about maximal length LFSRs and their state generation properties
  • Explore practical applications of LFSRs in cryptography and error detection
USEFUL FOR

Digital circuit designers, cryptography enthusiasts, and students studying digital systems who seek to understand the intricacies of Linear Feedback Shift Registers and their applications.

Weaver
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Homework Statement
The student decides to use a Linear Feedback Shift Register (LFSR) to
repeatedly step through each row of memory when performing DRAM
refresh. The memory has 2^7 rows. Design an LFSR circuit to perform this task.
Relevant Equations
[See table below]
243549


From this table:

  • Looking at the 7 row and taking the first entry, 1
  • This is 000001
  • Adding back the highest and lowest bit: 10000011
  • And then the equation would just be x^7 + x +1 ?

  • Or taking the taking the third entry, 7
  • This is 000111
  • Adding back the highest and lowest bit: 10001111
  • And so the equation is just :x^7 + x^3 + x^2 +x+ 1?

Is that correct?
 
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Weaver said:
Is that correct?
There is a trap for beginners with LFSRs, either the case of all ones, or that of all zeros is prohibited as the register locks if it enters that state.

An SFSR must be initialised to avoid an attempted start from the prohibited state.

What would happen if you used only 7 bits from an 8 or 9 bit maximal length LFSR, would that generate all 7 bit states equally from 0000 000X to 1111 111X ?
 

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