LTspice: Implementing a Single Balanced BJT Mixer

[SumDood_]

TL;DR Summary: Struggling to implement a BJT Mixer, which is part of implementing RADAR transmitting at 600MHz in LTspice.

I am attempting to implement RADAR in LTspice. At the moment, I am trying to implement the following three blocks that would make up the transmitter of the RADAR: power amplifier, Upconvert (Mixer), filtering.
I am trying to implement a single balanced BJT Mixer, but in doing, so, I am realising how much I don't know about what I am doing. I have access to an oscilloscope and function generator.
What I have done so far:

My Questions:
how do I know in which region are the transistors supposed to be biased in? Are transistors typically always biased in the same operating region if they are implemented as one block? Meaning, would a mixer's transistors all be biased to the same region? Is it acceptable to use the same bias signal to bias all the transistors?

How do I use the datasheets of transistors to bias them correctly? What parameters do I look at? How can I use the DC Operating Point analysis in LTspice to determine if the transistor is operating in the correct region? Is it a certainty that if the biasing is done correctly, it will be maintained when RF signals are injected into the circuit? What is the difference between transient and AC Analysis, how do I determine which analysis is the right one?

In LTspice, when simulating transistors, are parasitic capacitances part of the simulation as frequency increases?

In some designs, I see the use of Capacitors, and Inductors that are labelled as follows: RFC + BLK. My understanding is that these are referred to as RF Chokes and blocking capacitors. How are the values of these components determined? Are they necessary for simulation? How do I determine if I need a filtering circuit or tank circuit? Are these always connected towards the output of a given circuit design?

Thank you to anyone for helping me out. I realise a lot of this is quite rudimentary, but this has been quite a struggle for me.

 

[Baluncore]

Why do you need 600 MHz radar? GPR? You will need a licence to transmit radar signals on 600 MHz. I assume you are building pulse radar, have you considered chirp or frequency swept radar?

Meaning, would a mixer's transistors all be biased to the same region? Is it acceptable to use the same bias signal to bias all the transistors?

The same DC bias voltage goes to the bases of the differential pair, but they are decoupled with resistors to prevent RF crosstalk. The bias current is set by the lower BJT, Q1, with resistor R3, so the transistors will both be biassed on.

How can I use the DC Operating Point analysis in LTspice to determine if the transistor is operating in the correct region?

The DC operating point is computed by assuming all capacitors are open circuit, and all inductors are short circuits, so AC analysis can be ignored.
The transistors will be biassed by currents. Check their collector currents, they should be about half the total bias current sunk by Q1, which should remain linear and not cut off.

Is it a certainty that if the biasing is done correctly, it will be maintained when RF signals are injected into the circuit?

Only if the RF signal inputs are lower amplitude than the bias voltages. The differential pair needs to remain linear, so neither should be turned fully off by the RF.

What is the difference between transient and AC Analysis, how do I determine which analysis is the right one?

Transient analysis simulates the voltages and currents, then plots waveforms against time.
AC analysis plots signal phase and amplitude in dB, against log frequency.

In LTspice, when simulating transistors, are parasitic capacitances part of the simulation as frequency increases?

That will depend on the model used. It is easy to check. VHF and UHF transistors will definitely model capacitance. A generic "NPN" without a part number, may ignore capacitance. You are expected to control the model if it is critical.

RFC + BLK. How are the values of these components determined? Are they necessary for simulation?

They are selected as low-pass filters to keep RF out of the power supplies, so the output stage power variations cannot feed back to the input stages and cause oscillation. Values are selected to be more than sufficient, to block the nuisance signals that may be present. They are not necessary for simulation if your voltage supplies are very low impedance. If you have series R or L in your voltage sources, then you will need to include isolation components in the supply distribution.
In a real circuit you may have a tantalum 10 uF, in parallel with 0.1 uF ceramic cap, and a ceramic disc 100 pF close to a component. Together they each do their particular job in the real circuit with connection traces, but in LTspice they will all be added, unless you define their parasitic parameters.

How do I determine if I need a filtering circuit or tank circuit? Are these always connected towards the output of a given circuit design?

A tank circuit with high Q will not pass rectangular pulses of RF. Pulse radar circuits employ pulse shaping networks to maintain and enhance the sharpness of the pulses radiated.

Change the name of your LTspice.asc file to LTspice.asc.txt so you can attach it to your next post.

 

[SumDood_]

Thanks for your detailed response!
I will be going through your responses and improve my work where I can.

Why do you need 600 MHz radar? GPR? You will need a licence to transmit radar signals on 600 MHz. I assume you are building pulse radar, have you considered chirp or frequency swept radar?

This is actually a class project and the design is, for the most part, on me. The 600MHz frequency is arbitrary. If I manage to implement my designs, I would be demonstrating my work in a lab.

Unfortunately, I haven't thought much of the type of radar I am building. I don't really have an actual application in mind to guide that line of questioning. It is just a topic I thought was interesting.

Change the name of your LTspice.asc file to LTspice.asc.txt so you can attach it to your next post.

Will surely do that!

 

[SumDood_]

I am using the mixer for the purposes of upconversion. The LO is a signal operating at 400MHz, and the RF signal will operate at 200MHz.
From the output results, I am pretty sure I am wrong, and the circuit isn't working correctly. I believe the biasing may be incorrect.

Is it valid to use these equations to bias the BJTs?
$V_{BE} = 0.7V$ and $V_{CE} = 0.3V$.
Do the following equations make sense? I am referring to bias voltages as Vbias.
For Q1:
$V_{B} = V_{bias} - I_{B}R_{B}$
$V_{E} = I_{E}R_{E}$

The same equations are valid for Q2 and Q3 with the difference being that $V_{E2} = V_{E3} = V_{C1})$

 

[Baluncore]

It does not perform as expected because the bias voltage for the lower stage, Q1, is the same as the bias voltage for the differential pair, Q2, Q3.
Also, the LO, -LO signal is not connected to the pair.

You need to think in terms of current flow, not voltage when working with BJTs, but you must then make sure there is sufficient voltage compliance, headroom, where stages couple directly.

Your Q1 sets the bias current of the differential pair. Q1 base needs to be biassed sufficiently above ground, so it does not clip when driven by the LO = 10 mV input. You should lower the V4 bias voltage to about 2 volts, which will move the Q1 collector well below the differential pair emitter voltage. Then it should work. Adjust the R_e1 to set the bias current for the pair.
Differential pair I_bias = ( V_bias - V_be ) / R_e1.

When you plot the TR against time, also plot your bias voltages, so then you can see the signals do not clip due to stage bias voltage.

Is it valid to use these equations to bias the BJTs?

Vce = 0.3 V would be the saturation voltage of the BJT. While operating with signals, the collector voltage would be much higher. The best VHF performance avoids low Vce voltages because saturation slows the BJT down. Junction capacitance becomes very high when collector voltages are below one volt.

Before FFT, your TR plot should be longish in time, so when you show the FFT you will get good resolution and separation of the spot frequencies. You also need to take manual control of the FFT horizontal axis to get the spectrum in the window. When plotting the FFT of harmonic frequencies, use a linear scale for the horizontal axis, so they space equally. Once the horizontal scale is looking good, set the bounds for the vertical axis in dB, to eliminate unnecessary depth, i.e. cut the long grass off the noise floor, so only the tips show.
You may notice "alias" frequencies, where higher harmonics of the signal are folded back down, into the display below the highest frequency being plotted. Recognise and ignore them for now.

 

[Baluncore]

I have edited your schematic to get it to work. There is still more to do.

 

[SumDood_]

Thanks for this, I really appreciate it.
I kept re-reading your response trying to understand what I am doing wrong. My (incorrect) understanding has been that I need to bias the base of a transistor through a voltage and a resistor, which would then allow me to further use it for applications such as a mixer.
I'll try to study your implementation and see if I understand the changes you've made.

 

[Baluncore]

Here is another implementation. The bigger LO goes to Q1, while the smaller signal goes to the differential pair, which is normal practice with BJT mixers.

In the FFT, see how the 400 MHz LO is rejected by the mixer. In place of a centre-tapped primary output transformer, an LTspice Bv device subtracts the IF outputs, to convert differential to single sided for the FFT, or you would not see the cancellation of the LO in the simulation.

All bias voltages are derived from one chain of resistors. Notice how the signals are separated by voltage, so they operate without clipping, each with sufficient headroom.

 

[SumDood_]

I have been trying to bias my initial topology using a bias chain. I can't seem to push Q3 VCE. I have been unsuccessful as well when trying to reduce VE through RE1. I'd appreciate any advice in understanding what am I doing wrong. I believe Q1 and Q2 are biased correctly but Q3 isn't.

 

[Baluncore]

I can't seem to push Q3 VCE.

Your Q3 is saturated. That is because there is a DC voltage difference between the VB2 and VB3. The important thing about differential pairs, and balanced mixers, is symmetry. The same divider chain must provide the bias voltage to both Q2 and Q3, or it will not balance.

I have been unsuccessful as well when trying to reduce VE through RE1.

The voltage VE1 is controlled by the highest base voltage of the differential pair, not by the current being sunk by the Q1 collector.

Maybe you are not thinking like a BJT.
Set the base voltage of the NPN transistor.
Think of the base-emitter as a forward biassed diode.
The emitter voltage will be about 0.7 volt below the base.
The current sunk from the emitter is decided by; Ie = Ve / Re.
Of the current supplied from the emitter, 1% will come from the base, 99% will come from the collector.
The collector just sinks the current needed.
Vc is determined by the collector circuit load resistance.
Vc = Vsupply - Ic * Rc .

For Q1, Vb1 is set at about 3 V.
Ve1 will be about; (Vb1 - 0.7) = 2.3 V.
The voltage across Re1 will be Ve1, so; Ie1 = Ve1 / Re1.
For Q1; Ic1 = Ie1 - Ib1.
Ic1 will be sunk equally from the emitters of Q2 and Q3.
So they will have; Ie2 = ½ Ic1 each, when balanced.
Note that; Vb for Q2 and Q3 is set to 6 V, well above the Q1 base voltage.
We can assume that Ic2 ≈ Ie2;
Then; Vc2 = Vcc - Ic2 * Rc2 .

 

[SumDood_]

So I have managed to bias correctly, but the IF output from Bv is not expected. Though, the voltages look good to me.
Do you see what I am missing?
One thing that I would appreciate you expanding on is the RF gain capacitor and why it helps with RF gain.

 

[Baluncore]

Your +LO and -LO are shorted together by the use of the same label VB2.
Change VB2 on the Q3 base to VB3.
The LO current would have been very high.
Edit.
I cannot check it because you re-attached the older Mixer_V3.as.txt

 

[SumDood_]

Oh sorry about the file, here is the correct one.
Edit: It seems to be working now, but I am kind of confused. I was using the net label VB2 so that both Q2 and Q3 are biased in the same manner. But I changed VB2 to VB3 and Q3 is still working? Like, didn't I just remove the DC biasing by removing net label VB2?

 

[Baluncore]

But I changed VB2 to VB3 and Q3 is still working? Like, didn't I just remove the DC biasing by removing net label VB2?

That is because your ±LO, (AC voltage source), was kind enough to do that DC biasing for you. If you had a DC offset in the ±LO source, it would not have worked.

Symmetry is important in the real implementation. The ±LO will probably be the secondary of an RF transformer. Then the transformer will be centre tapped, or it would employ two equal value bias resistors from the same voltage source.

You are still operating with your low-amplitude signal to Q1, and the high-amplitude LO to Q2,3. In post #8, I showed how to flip that.

Then you will have better gain and linearity in the small signal path, and by removing Ce from Q1, better linearity for the LO.

One thing that I would appreciate you expanding on is the RF gain capacitor and why it helps with RF gain.

The resistor, Re1, sets the differential pair bias current, the AC gain of Q1 is set by the lower reactance of Ce1, without influencing the bias current. The technique is called emitter-degeneration.
https://en.wikipedia.org/wiki/Common_emitter#Emitter_degeneration
https://www.electronics-tutorials.com/amplifiers/emitter-degeneration.htm

 

[SumDood_]

I have made a few changes and implemented a differential amplifier that seems to be working. Now, I have an issue with passive filtering. I am trying to implement a band-pass filter that is centred around the IF. It seems to be not acting as a band-pass filter but attenuating the output signal into uV.
Also, CE at Q1, seems to be helping with reduced noise.

Without Filtering:

With Filtering:

 

[Baluncore]

What frequency is your IF ?
Check the bandwidth of the OP07 op-amp.

The op-amp difference voltage will be near DC zero volts, which is too close to the negative supply rail.
Quick fix, do not connect OP_R4 to ground, connect it to VB2, then op-amp signals will be near mid-supply.

Your passive BPF is centred on 100 kHz, but there is no signal that low in frequency.

 

[SumDood_]

The IF frequency is 90MHz.
I changed the op-amp to one that is more suitable. Though, there is still significant attenuation after I pass the differential output through a filter. If I connect VB2 instead of ground, the FFT is much noisier. Not sure if that is worth it.
What is a bit confusing is that the filter doesn't seem to be working as intended.

 

[Baluncore]

Your simulation is now so far from reality, that it is more a work of art than engineering. Your project has lost touch with reality, it has become a house of SPICE cards.

If I connect VB2 instead of ground, the FFT is much noisier. Not sure if that is worth it.

It is noisier because the op-amp is functioning, rather than being driven hard against a supply rail. You need to check the range of input voltages that can be sensed by the op-amp, and the range of output voltages that can result.

No engineer would use an op-amp in that situation. They would use a transformer with a centre tapped primary, then integrate the secondary into the following BPF. The modest amplifier gain could be obtained by changing the turns-ratio of the transformer.

What is a bit confusing is that the filter doesn't seem to be working as intended.

That is because it is designed for the wrong IF frequency. The BPF is also a passive RC filter, which has a significant in-band loss. Signal is too valuable a resource. It should not be thrown away so carelessly.