Max Clock frequency with a Flip-Flop

[Number2Pencil]

I need to know the max clock frequency of two identical J-K flip flops linked together (the first flip flop has HIGHs running into its inputs, and the second flip flop has the outputs (Q and Q bar) running to its inputs). They share a common clock.

The data sheets say the prop delay (low to high and high to low) is 5 nano seconds, and the set-up time is 2 nano seconds. the max frequency is usually just given, but this time it's not.

would it be 1/5nano seconds, 1/2 nano seconds, or 1/7 nano seconds?? I can't figure it out...

 

[berkeman]

There will be a setup and hold time specified for the FFs, as well as propagation delays from input to output. If you draw a timing diagram, you will need to ensure that the setup and hold times are met for both FFs. So if they are linked in series, the output of the 1st FF must not change before the hold time of the 2nd FF is met. So the minimum prop delay through the first FF must not be shorter than the hold time requirement of the 2nd FF. And the max clock rate is limited by the delay of the 2nd FF and the worst-case setup time of the 2nd FF.


EDIT -- fixed a couple typos

 

[Number2Pencil]

so combining what you said with what I have:

--Qa must not change faster than 2 ns
--the minimum prop delay through 1st must not be shorter than hold time. True: prop delay = 5 ns, hold time = 2 ns

--max clock rate = 5 ns...worst-case: max clock time = 2 ns


so the maximum clock rate would be 2 ns?

 

[berkeman]

so the maximum clock rate would be 2 ns?

No. You need the data to get through the first FF and be stable for the setup time before you can provide the next clock edge that will clock the FFs (whichever it is that clocks the flop, rising or falling).

 

[Number2Pencil]

after making some timing diagrams, I tried a little algebraic approach:

clock peroid - 5ns >= 2ns
clock peroid >= 7ns

 

[berkeman]

Looks right to me, at least for a straghtforward hookup of two FFs. Good job.