Asynchronous Counter 4-bit Output Frequency

[jaus tail]

Homework Statement

[/B]Y is output of rightmost flip flop. Q

Homework Equations

Drawing Timing Diagram. F(o/p) = F(clock)/(number of stages in output)

The Attempt at a Solution

The last flip flop has positive triggering clock. The moment Flip Flop output becomes 110X with MSB being rightmost flip flop, all flip flops gets cleared to 0 output.

So number of stages is 4. So F(o/p) = F(clock)/4 = 2.5KHz. Book answer is A). 0.833 which means they got 12 stages. How? Is my timing diagram wrong or correct?[/B]

 

[berkeman]

What is the signal going into the middle bottom of each FF? Is it supposed to be lined up with the Clr- input? How does that affect your diagrams?

 

[Baluncore]

So number of stages is 4. So F(o/p) = F(clock)/4 = 2.5KHz. Book answer is A). 0.833 which means they got 12 stages. How?

Each JK F-F changes state when clocked. That means it divides the clock frequency by two.

The frequency of Q1 will be clock / 2.
The frequency of Q2 will be Q1 / 2 = clock / 4.
The frequency of Q3 will be Q2 / 2 = clock / 8.
The frequency of Q4 will be Q3 / 2 = clock / 16. (But is triggered on the rising edge).

So four stages can divide the clock frequency by 2⁴ = 16, not by 4.

How many clock edges occur before the NAND gate output goes low and the pattern repeates?

 

[jaus tail]

As per the clear signal, when the input of Nand gate is 110, then it will send a clear pulse to all the JK flip flops and then they will give output as 0, so after 110, the stage becomes 0000
So I got following states:
0000
0001
0010
0011
1100 (since the 4th Flip Flop is positive edge, so moment 3rd flip flop output goes from 0 to 1, the fourth flip flop will also go from 0 to 1)
Now this 1100, will reset the Nand output to 0, and that will send clear command. So output becomes 0000.
So there are only 4 stages that are underlined above.
So output frequency should be f(clock)/4
It would be f(clock)/16 if there were 16 stages. As per timing diagram also i am getting output frequency as f(clock)/4
Here is the timing diagram.

The negative edge is in blue color. For FF/3 the positive edge is in blue color as that activates FF/4.

In yellow region, the output of FF's becomes 1100--MSB being right most FF. This sends clear command to Flip Flop via Nand gate, so output becomes 0000. Assuming T(delay) of Nand gate is very less as compared to Time period of FF.

 

[Baluncore]

It is clear that there must be an error in the diagram, or the answer. A divide by 4 circuit could be implemented by a ripple counter using only two JK F-Fs, so the diagram is probably wrong, with the answer correct.

There is one change we can make to the diagram that will divide the 10kHz clock by 12 to get 0.833 kHz.
That change is to restore the Q4 clock to negative edge triggering like Q1, 2 & 3.
Then arrival at the 12'th state will cause an asynchronous reset to state 0 through the NAND gate.

 

[jaus tail]

Yeah. The Timing diagram looks like this then:

 

[Merlin3189]

Apologies if anyone read my earlier post before I deleted it. I failed to notice the missing inverter!

What I'd like to ask OP or anyone, is about the convention for drawing the JK FF symbol, particularly the clock input.

Since the question states the J and K inputs are held high and the clock is roughly equal mark:space ratio, I assume these must be master-slave JKs to avoid race toggling. If so, I think the normal sequence is to latch the inputs on the rsing edge and switch the outputs on the falling edge.
I don't think it would make any difference to the operation if the clock were inverted, except to alter the significance of the clock phase - Q transition occurring on the rising edge rather than on the falling edge.

So my query is, what is the significance of the inverter on these clock inputs?
And if it is simply to show that the clock is inverted, shouldn't the Q transitions be shown on the rising edge in this solution?

Incidentally, I checked the cct as printed for both interpretations of the clock. Transition on the rising edge leads to 11 states rather than the 4 states using the falling edge. So 11 is still wrong, but at least it is a plausible solution for a 4 stage counter.

 

[Baluncore]

Incidentally, I checked the cct as printed for both interpretations of the clock.

JK flip-flops are so last century, the 1970s to be precise. They bridged the transition between simple level controlled RS flip-flops and edge triggered D type flip-flops.

The idle input voltages being tied high, and the negative logic control signals, indicate TTL signals. That makes it an industry standard 7473 or 7476, built internally from NAND gates and being toggled on the high to low transition of the clock.

The early D flip-flops, (such as the 7474 that evolved from the JK), toggled on the rising edge of the clock, which became the standard for TTL D type data registers.

As a fossilised learning exercise, we can assume that JK flip-flops toggle on the falling edge of the clock.

 

[jaus tail]

The zero before the clock input means its falling edge triggered.

 

[Merlin3189]

Thanks for that.
My doubt came from the fact that this (falling edge switching) was to me "normal", so adding the inverter (that circle normally inverts the polarity of a signal) suggested something different.
As Baluncore suggested, I played with these things a long time ago, but my recollection is that people had differing opinions about the schematic symbols, so I used to check manufacturers'data sheets very carefully to see how the paticular chip worked.

Incidentally, my casual comment about inverting the clock making no difference turns out to be wrong. Switching on the falling edge it counts up and on the rising edge counts down. As a free running divider it would still give the 16 counts, but the gated reset causes it to count down from 0000, 1111, 1110, 1101, then reset, giving only a 3 count.