MOS capacitance when Vgs is negative

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SUMMARY

The discussion focuses on the behavior of MOS capacitance, specifically Cgs and Cgd, when the gate-source voltage (Vgs) of an NMOS transistor becomes negative. When Vgs is negative, the NMOS enters depletion mode, leading to a reduction in capacitance due to the formation of depletion regions around the source and drain. The capacitance is primarily influenced by Csb and Cdb, which are in series with Cgb. As Vgs decreases further into accumulation mode, the gate-bulk capacitance increases, and all capacitances (Cgb, Cgd, and Cgs) become effectively parallel due to the low-resistance channel.

PREREQUISITES
  • Understanding of NMOS transistor operation and modes (depletion and accumulation).
  • Familiarity with MOS capacitance concepts, including Cgs, Cgd, and Cgb.
  • Knowledge of the effects of gate voltage on channel formation in MOSFETs.
  • Basic principles of RC networks in electronic circuits.
NEXT STEPS
  • Study the impact of negative Vgs on NMOS transistor characteristics in detail.
  • Learn about the formation and effects of depletion regions in MOSFETs.
  • Explore the mathematical modeling of capacitance in MOSFETs under different operating conditions.
  • Investigate the design implications of gate-bulk capacitance in integrated circuits.
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Electrical engineers, semiconductor device designers, and students studying MOSFET operation and capacitance effects in electronic circuits.

iVenky
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I have a question on what happens to MOS capacitance Cgs+Cgd, when Vgs goes negative in the NMOS shown. I see that when Vgs goes negative, the channel is full of holes because of p- substrate, which means we see the Cox capacitance (without any other capacitance in series), but I am not sure if this is between Cgs (or Cgd) or Cgb. My intuition says it's between Cgb, but if that's the case, then there is no capacitance between Cgs (or Cgd), ignoring the overlap capacitance.
Attached the figure here

https://imgur.com/a/LPlIcKX
 
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iVenky said:
I have a question on what happens to MOS capacitance Cgs+Cgd, when Vgs goes negative in the NMOS shown. I see that when Vgs goes negative, the channel is full of holes because of p- substrate, which means we see the Cox capacitance (without any other capacitance in series), but I am not sure if this is between Cgs (or Cgd) or Cgb. My intuition says it's between Cgb, but if that's the case, then there is no capacitance between Cgs (or Cgd), ignoring the overlap capacitance.
Attached the figure here

https://imgur.com/a/LPlIcKX
The capacitance (between gate and source/drain) of NMOS in depletion is reduced because no channel mean Cgb is in series with Csb+Cdb.
with negative voltage, the capacitance is limited by Csb+Cdb, and reverse proportional to square root of voltage between gate and drain/source - because of depletion regions forming around source/drain
 
Actually when you apply a small negative voltage to the gate the device enters a depletion mode and in that mode what Trurle said is true. But then if you decease the Vgs even lower the device enter the accumulation mode and the gate-bulk capacitance increases again back to the same value that it had in the inversion mode (when Vgs>Vth). In the accumulation mode in the first approximation (neglecting the channel resistance) the drain and source are shorted through the low-resistance of the channel so all capacitors Cgb, Cgd and Cgs are connected in parallel. In a more accurate approximation you have a distributed RC-network across the channel.
 

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