My Static RAM Cell I Made over the Weekend

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LtIvan
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Allo,
Recently, I have been researching RAM, including formats such as DRAM and SRAM.
While I was running simulations on SRAM one week, I realized I could make a 1 bit Static Memory Cell using a simple Schmidt NAND IC.
I ran a draft for it displaying two feed backing NAND gates as inverters, and just one bitline connecting a SPDT to 4.5V and 0V.
I did this as just as an experiment to see if two NAND gates can be used to make a memory cell.

The supply voltage and Vdd is 4.5, (three AA batteries). The IC is 493B Quad Schmidt NAND. The capacitor is used as a safety charge for the CMOS circuitry. the two switches are basic SPDT ones I found lying around. The PCB is a spare Jaycar project I had and is irrelevant to the design.

When SW1 is on and SW2 is connected to 4.5V, you add 1 bit (4.5V) to the the memory cell node. When you turn SW1 off, the NAND node hold 1 bit. The same can be said vice versa when storing 0 bit when SW2 is connected to ground.

In fig.5, the multi-meter measures 4.44V (≈4.5, accepted tolerance of accuracy) across the node between IC1a output and SW2 to ground, when there is 1 bit stored; similar testing has shown 0V when 0bit is stored.

The figures attached show several examples of typical SRAM, (fig.1, fig.2); another figure shows a draft design on AutoCAD, (fig.3); other figures show photos of the actual design.

I'll be soon uploading a PCB design.

Hopefully with this, I could make an array of several memory cells.

Please reply feedback,

Thanks in advance,
 
Attachments
  • Circuit schematic of a six-transistor SRAM cell with word line WL at top, bit lines BL and BL-bar at bottom, pass transistors M5 and M6, cross-coupled inverters M1 to M4 powered by VDD, storage nodes Q and Q-bar.
    sram.png
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  • Circuit schematic of a six-transistor SRAM cell: two cross-coupled inverters between nodes Q and Q-bar, with access transistors M5 and M6 gated by word line WL connecting to bit lines BL-bar and BL.
    sram1.png
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  • Circuit schematic titled NAND Gate Memory Cell Draft: two Schmitt NAND gates IC1a and IC1b cross-coupled as inverters, +9V supply, switches SW1 and SW2, and capacitor C1 across the supply, with a parts table at top right.
    NANDSRAM.png
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  • Hand-drawn schematic on paper behind a breadboard-style green PCB with an IC, two slide switches, a potentiometer and a three-AA battery holder with red and black leads.
    WIN_20161010_13_13_11_Pro.jpg
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  • Photo of a breadboard-style test setup: an orange digital multimeter reading 4.44 on its LCD beside a green circuit board with a DIP chip, a small slide switch and red and black test leads.
    WIN_20161010_13_16_08_Pro.jpg
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Discussion

It's not good practice to short circuit the output of a logic gate to ground or VCC. Sure it may work if you use switches but it might not work if you use a logic gate instead of switches.

Take a look at an SR latch.
 
CWatters said:
It's not good practice to short circuit the output of a logic gate to ground or VCC. Sure it may work if you use switches but it might not work if you use a logic gate instead of switches.

Take a look at an SR latch.

Thanks for thy feedback,

You are correct; it is not a good practice to connect the voltage supply to any other nodes. Since it can short the circuit, and damage some of the components.
However, this was an experiment to see Schmidt NAND gates can be used for a SRAM latch or memory cell. Also, the application of this will be an array of these, and the voltage supply will be separated with a suitable set of buffers.

The reason I do not want to use SR latch or a flip flop bistable latch is I want to research some of the conventional memory cell types of RAM.

I am hoping to make a small model of an array of SRAM cells; however, I want to know should I use the typical inverters or FETs as the configuration of a SRAM cell. For example, in my case, FETs on a PCB will take up room.

Please reply feedback,

Thanks in advance,
 
LtIvan said:
I want to know should I use the typical inverters or FETs as the configuration of a SRAM cell.

It's hard to give feedback without knowing your purpose and objectives for doing this project. What do you mean by "research"? Seems like a lot of work for potentially little reward? What do you hope to learn that can't be learned by reading the wiki page on SRAMs?

There are several of ways to make a simple bistable using transistors, FETs or logic gates. These are available in a wide range of different packages some of which are very small. Which ends up smallest might depend on what tools you have to assemble the PCBs. The switches could well take up more space than the electronics.
 
Firstly, I have not had the time to purchase a breadboard yet; I was going to the other day when I was in Jaycar, but hesitated at the price and my spending budget.

One question I have might seem simple, but want to make sure, there is no need to bolt the tab/body/substrate to ground for the access MOSFETs connecting the wordline and the bitline? I thought there wasn't any need to until I stubble across this diagram.

In the attachment, notice the body is connected to ground?

Does this mean the hole needs to be bolted to a ground terminal?

Thanks in advance,
 
Attachments
  • Circuit schematic of a 6-transistor SRAM cell with cross-coupled inverters p-left, n-left, p-right and n-right, access NMOS transistors to bit lines BL and BL-bar gated by word line WL, and nodes labelled Vl,out, Vl,in, Vr,in and Vr,out.
    mosfet.png
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Check the data for the FET you plan to use.

Frequently the heat sink tab is connected to either the drain or source inside the device. This can sometimes cause problems if multiple FETs are bolted to the same heat sink. The heat sink can end up shorting one part of the circuit to another. Means you sometimes need insulating mica washers between the tab and heat sink .

However you don't really need a power device for this. Perhaps look at a lower power "logic level" FET in a smaller package?