Need Explanation of this Master Slave D Flip Flop

[u_know_who]

Please look @ the pictures below. I have drawn a master slave D flipflop with preset and clear option as mentioned in the book.

http://i28.lulzimg.com/7e22bfc016.png

Can anyone tell me what is the necessity of the wires that are highlighted in the image? isn't the wire @ last stages of NAND gates enough?

 

[Floid]

The pairs of U5+U6 and U7+U8 both form memory elements. So if you really want to preset or clear the entire circuit you most do that action on both memory elements. If you only did it to U7+U8 then you could force the desired output, but as soon as you release the preset or clear the circuit would just revert back to whatever was stored in U5+U6.

 

[u_know_who]

The pairs of U5+U6 and U7+U8 both form memory elements. So if you really want to preset or clear the entire circuit you most do that action on both memory elements. If you only did it to U7+U8 then you could force the desired output, but as soon as you release the preset or clear the circuit would just revert back to whatever was stored in U5+U6.

Hmm, i think that's the answer of my question. Thank you. :)

 

[u_know_who]

Well after studied what i have found that it is a must. You can't set ouput 0 by pressing clear = 0 when the slave is active (clock = 0) unless u give those connection that i mentioned.