JK Master-Slave Flip-Flop timing diagram

  • Thread starter JasonHathaway
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In summary: The JK FF is a combination of a JK Latch and a D Latch. It's a little confusing in the OP's schematic since the master FF is never clocked.
  • #1
JasonHathaway
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Homework Statement


Draw the output Q of the JK Master-Slave Flip-Flop

Homework Equations


Master works at the rising edge, while and the Slave works at the falling edge.

The Attempt at a Solution



http://s13.postimg.org/j5ldpmw9i/20150109_095656.jpg
 
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  • #2
JasonHathaway said:

Homework Statement


Draw the output Q of the JK Master-Slave Flip-Flop

Homework Equations


Master works at the rising edge, while and the Slave works at the falling edge.

The Attempt at a Solution



http://s13.postimg.org/j5ldpmw9i/20150109_095656.jpg

Could you post the schematic for the J/K M/S flipflop you are using for this problem please? Thanks. :)

EDIT -- And were you given the J & K waveforms as part of the problem statement?
 
  • #4
EDIT waveforms look okay

On the rising edge of clock pulse #1 (CP#1), your figure shows J=0 & K=1
subsequently on the falling edge of CP#1 this sets Q to 1.

That is not what I was expecting of a JK FF.
Are you sure that is right?
 
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  • #5
The first part is OK. (Q is not defined by the inputs before clk 1 falling edge). The master is at J=1, K=0 which on that edge is transferred to the slave, so Q1 = 1 upon the falling edge of clk1.

The J input at the falling edge of clk3 should not coincide with that clock edge. There needs to be a minimum setup time on J before that edge occurs. However, assuming J is still high when the clk3 edge occurs, that Q wavform is also correct (toggle action).

The same problem obtains at the falling edge of clk5. What did the master latch?

Bottom line: inputs must be stabilized at least several ns before a clock falling edge. This is the only timing requirement for a master-slave FF. Timing of the inputs is not important for the rising edge of any clock pulse since the master FF output is immaterial until the clk drops.
 
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  • #6
After closer scrutiny, I agree with rude man. JasonHathaway's sketch of waveforms is correct. (I'd forgotten that for the Master, it's not "edge triggered" as such. Level triggered would be more accurate.) The question of JK inputs changing coincident with the fall of the clock pulse is also a caution that should be heeded.

However, none of us is correct if the gating arrangement in the linked .gif is used, because it interposes an inversion between the Master and the Slave.
 
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  • #7
NascentOxygen said:
After closer scrutiny, I agree with rude man. JasonHathaway's sketch of waveforms is correct. (I'd forgotten that for the Master, it's not "edge triggered" as such. Level triggered would be more accurate.) The question of JK inputs changing coincident with the fall of the clock pulse is also a caution that should be heeded.

However, none of us is correct if the gating arrangement in the linked .gif is used, because it interposes an inversion between the Master and the Slave.
Probably a typo on the master FF outputs. Should look same as the slave.
In any case, the OP's schematic is inadequate. The circuit should be shown in terms of gates; see attached.
 

Attachments

  • M-S J-K FF.pdf
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Related to JK Master-Slave Flip-Flop timing diagram

1. What is a JK Master-Slave Flip-Flop?

A JK Master-Slave Flip-Flop is a type of digital circuit made up of two interconnected flip-flops that work together to store and transfer data. It is commonly used in sequential logic circuits to store and synchronize data.

2. How does a JK Master-Slave Flip-Flop work?

The JK Master-Slave Flip-Flop consists of two parts - the master flip-flop and the slave flip-flop. The master flip-flop takes in the input data and the clock signal, and the slave flip-flop stores the output data. The clock signal controls when the data is transferred from the master to the slave flip-flop. The JK inputs determine whether the data is stored or inverted in the slave flip-flop.

3. What is the purpose of a timing diagram for a JK Master-Slave Flip-Flop?

A timing diagram for a JK Master-Slave Flip-Flop is a graphical representation of the timing relationships between the input and output signals. It helps to visualize and understand the behavior of the flip-flop in response to clock signals and input data changes.

4. What are the important components of a JK Master-Slave Flip-Flop timing diagram?

The important components of a JK Master-Slave Flip-Flop timing diagram include the clock signal, input data, output data, and the timing relationship between these signals. It also includes the setup and hold times, which are the minimum times the input data must be stable before and after the clock edge for proper operation.

5. How is a JK Master-Slave Flip-Flop timing diagram interpreted?

A JK Master-Slave Flip-Flop timing diagram is interpreted by following the timing relationships between the clock signal, input data, and output data. The clock signal controls the timing of data transfer, and the input data determines whether the output data is stored or inverted. The setup and hold times must also be met for proper operation of the flip-flop.

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