# JK Master-Slave Flip-Flop timing diagram

1. Jan 9, 2015

### JasonHathaway

1. The problem statement, all variables and given/known data
Draw the output Q of the JK Master-Slave Flip-Flop

2. Relevant equations
Master works at the rising edge, while and the Slave works at the falling edge.

3. The attempt at a solution

http://s13.postimg.org/j5ldpmw9i/20150109_095656.jpg

2. Jan 9, 2015

### Staff: Mentor

Could you post the schematic for the J/K M/S flipflop you are using for this problem please? Thanks. :)

EDIT -- And were you given the J & K waveforms as part of the problem statement?

3. Jan 10, 2015

### JasonHathaway

4. Jan 11, 2015

### Staff: Mentor

EDIT waveforms look okay

On the rising edge of clock pulse #1 (CP#1), your figure shows J=0 & K=1
subsequently on the falling edge of CP#1 this sets Q to 1.

That is not what I was expecting of a JK FF.
Are you sure that is right?

Last edited: Jan 14, 2015
5. Jan 13, 2015

### rude man

The first part is OK. (Q is not defined by the inputs before clk 1 falling edge). The master is at J=1, K=0 which on that edge is transferred to the slave, so Q1 = 1 upon the falling edge of clk1.

The J input at the falling edge of clk3 should not coincide with that clock edge. There needs to be a minimum setup time on J before that edge occurs. However, assuming J is still high when the clk3 edge occurs, that Q wavform is also correct (toggle action).

The same problem obtains at the falling edge of clk5. What did the master latch?

Bottom line: inputs must be stabilized at least several ns before a clock falling edge. This is the only timing requirement for a master-slave FF. Timing of the inputs is not important for the rising edge of any clock pulse since the master FF output is immaterial until the clk drops.

Last edited: Jan 13, 2015
6. Jan 14, 2015

### Staff: Mentor

After closer scrutiny, I agree with rude man. JasonHathaway's sketch of waveforms is correct. (I'd forgotten that for the Master, it's not "edge triggered" as such. Level triggered would be more accurate.) The question of JK inputs changing coincident with the fall of the clock pulse is also a caution that should be heeded.

However, none of us is correct if the gating arrangement in the linked .gif is used, because it interposes an inversion between the Master and the Slave.

Last edited: Jan 14, 2015
7. Jan 15, 2015

### rude man

Probably a typo on the master FF outputs. Should look same as the slave.
In any case, the OP's schematic is inadequate. The circuit should be shown in terms of gates; see attached.

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