Dismiss Notice
Join Physics Forums Today!
The friendliest, high quality science and math community on the planet! Everyone who loves science is here!

Need serious advice on digital project problem

  1. Nov 13, 2006 #1
    first off I'm not looking for ANYONE to do the work for me, I have already spent 3-4 hours a day for the last 6 days on this and I'm stuck. It should be easy but something screwy is going on...


    Here are the project specifications: Using a SN74LS193 TTL IC, (an up/down counter with a dual clock input and a clear), create and counter that counts from 3 to 7 then repeats itself indefinently, FORWARDS or BACKWARDS. There will be a Mode switch for switching between counting up and counting down, as well as a reset switch that resets the counter to 7. The reset must be Synchronous with the clock even though the Load input on the IC is Asynchronous.


    So I designed it using logic to control what appears on the Load-Data Inputs (specifically the C input as this determines whether to load a 3 or a 7 in binary), and logic to control when a signal is HIGH. I connect this signal to an active-LOW preset input on a D flip-flop making the preset inactive when it's a 3 or 7, and sending a low through D to the Q output, connecting that Q to the active-low Load of the counter (thus, it's synchronous).

    You can look at my poorly drawn schematic for a better picture (maybe).

    The problem I'm having is that the LOW sitting on the D input of the flip-flop is NEVER getting sent through to Q during the down count when it's connected to LOAD of the counter (thus, never activating a LOAD to cycle back through the numbers). BUT, if I disconnect the Q output from the LOAD of the counter and place it on a random unused hole on my bread board, it works FINE! Why on Earth is the Load input driving this signal HIGH???

    If you're thinking "well your IC could be damaged". I tried using a different one and had the exact same problem!

    I'd appreciate any advice on this matter. There are some pictures attached proving this case. I can't prove that the clock is ticking on the Flip-Flops but I can assure you they were. and the D input is LOW on both pictures (it's kind of hidden behind some wires)

    thanks
     

    Attached Files:

  2. jcsd
  3. Nov 14, 2006 #2
    Well I found a way around it using a J-K flip flop!

    thanks for all the help (j/k)

    Now I have a new problem:

    I'm supposed to display the number on a seven segment display, so I'm using a BCD-to-7seg converter. The problem is that the outputs on the code converter are not changing no matter what's on the inputs. I checked the data sheets and made all the light-tests and other things inactive, but it's still not doing anything. I took the IC to a tech shop and they told me there is nothing wrong with my chip...

    any help on THIS matter?
     
  4. Nov 15, 2006 #3
    with a BDC to 7 Seg converter, with 0's on the input, you should read '00' on the outputs, sounds like mabey your 7 Seg driver circuitry is not correct, is the conver OPEN Collector outputs, and if so, do you have to correct pullup resisters. ??

    yes, you should tie unused I/O to GND, but u should read SOMETHING on the 7 seg, even rubbish.. nothing tells me you have a "system wide" problem, probably power supply related. ?? mabey..
     
  5. Nov 15, 2006 #4
    Yeah I just realized that I had to invert the outputs of the BCD to 7 Segment decoder before I put them in the 7 segment display (i busted a couple segments :(....)

    My NEWEST problem:

    The counter I'm using has a UP and DOWN input driven by a clock. When one "mode" is being driven, the other mode must stay at a HIGH. I have this driven by a mode switch as well (ANDed with the clock), and I noticed that if I change the mode switch at JUST the right time, there will be a moment in time (i think) where a LOW will appear on both inputs..screwing the counter up, and sending it into a random number.

    I guessed it's either that or somehow there's some quick spikes making it trigger a count a bung-hole load of times.

    I thought maybe I can use a 1 shot to clean up this problem: if the mode switch is switched, the one shot will trigger a high pulse for a short amount of time keeping it high while it changes modes...

    I'm having trouble using my one shot (74123), I've never actually used one and I am getting a constant HIGH on the output...

    can someone help me figure out how to hook one up, OR tell me a good solution to my problem?
     
  6. Nov 15, 2006 #5

    NoTime

    User Avatar
    Science Advisor
    Homework Helper

    Did you connect a time constant capacitor to the 123?
     
  7. Nov 16, 2006 #6
    yes i've connected them as shown in the data books...the only problem is I dont have many different capacitors, i've tried using different ones and connecting some in parallel to combine them....hasn't worked, I keep getting a high on the output...

    is it possible I have it set to have Tw delay last.......TOO long?
     
  8. Nov 16, 2006 #7

    NoTime

    User Avatar
    Science Advisor
    Homework Helper

    Since the output is high, then yes, it seems possible.
    High should only remain for the time constant.

    Also you might have a leaky capacitor.
    Electrolytic types are not a good choice.
     
  9. Nov 16, 2006 #8
    i calculated Tw, it says it should only stay high for 20 nano-seconds...hmm....dagum TTLs giving me problem after problem

    I really wish I was allowed to do this in VHDL...man would that be a pleasure cruise
     
  10. Nov 16, 2006 #9
    I have no clue how to make this thing glitch free....one shots didn't help...

    you switch the mode switch and it jumps off into a wild number.....who knew a digital project so idiotic and useless could just tear me apart...I can't even fathom trying to make something that's complicated and useful.

    someone throw me a bone here so I can get this class over with and change my major
     
  11. Nov 21, 2006 #10
    i have not drawn out your circuit, and put in the 1's and 0's (yet).

    but on first look, i think your problem might be due to the proporgation delay introduced, by the Inverter, in the input to the second AND gate, going to the DOWN pin.

    from your Mode selection line, this would make each AND gate change its mode at different times. so the length of your glitch may be equal to the delay of the Inverter.

    you may be able to delay the CLOCK, by running it through a couple of spare inverters, so (hopefully) the mode will always change when the clock is high.

    or you could use the clock the "ENABLE" mode selection, so the mode could only be changed on a leading or falling edge on the clock. which is kinda what your trying to do anyway.
     
  12. Nov 21, 2006 #11
    when your Mode goes from 0 to 1, on the rising edge, the AND gate with the Inverter on the Input from MODE.

    the OUTPUT of the inverter will be 1 until the mode leading edge proporgates through the inverter.

    this means that for this period of time, both AND gates will have a "1" on the Mode INPUT, UNTIL, the inverter catches up.

    this will place a 1 on both the UP and DOWN inputs for a brief time. and i guess the output of the counter is indeterminate with both I/P's are 1.
     
  13. Nov 21, 2006 #12
    what i think you need to do is to synchronize the clock with the mode selection.

    so you cannot change the mode until the clock is zero, or you cant change mode with clock is 1.

    if you inverted the clock signal, and AND'ed it with the MODE line, when the clock is 1 NOTClock is 0, and the output of the AND will be 0.

    possibly..
     
Know someone interested in this topic? Share this thread via Reddit, Google+, Twitter, or Facebook

Have something to add?



Similar Discussions: Need serious advice on digital project problem
  1. Project advice (Replies: 2)

  2. Digital Clock Project (Replies: 13)

Loading...