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New logic optimization algoritm

  1. Aug 3, 2010 #1

    I have an idea for new logic optimization algoritm, like "Quine–McCluskey algorithm" and the "Espresso heuristic logic minimizer", but it can handle multi-level representations and it can find the (theoretical) best circuit. It should work for 8 to 12 input bits. I was wondering if such an algoritm has useful applications and if it is worth the effort to make it. Can someone give his or her thoughts on it?
  2. jcsd
  3. Aug 4, 2010 #2
    Nowadays, logic optimization is more than finding the theoretically best logical circuit. You need to consider the fanout, gate size, delay for each cells, power consumption, end-to-end overall delay......
    But having a good algorithm is a must and if you have one, you have a great chance although I think 8 to 12 bit limit is too small(Imagine, one verilog module usually has hundreds of ports)
    And the recent trend is more for physical synthesis..i.e. taking the physical locations into account upon the synthesis and optimization. Synopsys, Magma, and probably Cadence all are doing it..

    I'd say keep working. If your tool is good enough, not necessary the best in the industry, someone may want to use it if the cost performance is right.
    You might be able to beat Synopsys some day if you refine your idea,, who knows.
    Last edited: Aug 5, 2010
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