New logic optimization algoritm

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SUMMARY

The discussion centers on a proposed new logic optimization algorithm that aims to improve upon existing methods like the Quine–McCluskey algorithm and the Espresso heuristic logic minimizer. This new algorithm is designed to handle multi-level representations and optimize circuits for 8 to 12 input bits, addressing factors such as fanout, gate size, delay, and power consumption. While the current trend in logic optimization leans towards physical synthesis, the community acknowledges the potential value of a robust algorithm, suggesting that if the tool demonstrates cost-effectiveness, it may find a market despite competition from established tools like Synopsys and Cadence.

PREREQUISITES
  • Understanding of the Quine–McCluskey algorithm
  • Familiarity with the Espresso heuristic logic minimizer
  • Knowledge of circuit optimization concepts, including fanout and gate delay
  • Experience with physical synthesis techniques in electronic design automation
NEXT STEPS
  • Research advanced circuit optimization techniques beyond traditional algorithms
  • Explore physical synthesis tools and methodologies used by Synopsys and Cadence
  • Investigate power consumption metrics in digital circuit design
  • Learn about Verilog module design and its implications for circuit optimization
USEFUL FOR

Engineers and researchers in electronic design automation, circuit designers, and anyone interested in developing or improving logic optimization algorithms for digital circuits.

Peter0000
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hi

I have an idea for new logic optimization algorithm, like "Quine–McCluskey algorithm" and the "Espresso heuristic logic minimizer", but it can handle multi-level representations and it can find the (theoretical) best circuit. It should work for 8 to 12 input bits. I was wondering if such an algorithm has useful applications and if it is worth the effort to make it. Can someone give his or her thoughts on it?
 
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Nowadays, logic optimization is more than finding the theoretically best logical circuit. You need to consider the fanout, gate size, delay for each cells, power consumption, end-to-end overall delay...
But having a good algorithm is a must and if you have one, you have a great chance although I think 8 to 12 bit limit is too small(Imagine, one verilog module usually has hundreds of ports)
And the recent trend is more for physical synthesis..i.e. taking the physical locations into account upon the synthesis and optimization. Synopsys, Magma, and probably Cadence all are doing it..

I'd say keep working. If your tool is good enough, not necessary the best in the industry, someone may want to use it if the cost performance is right.
You might be able to beat Synopsys some day if you refine your idea,, who knows.
 
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