PMOS Working Concept: Vgs (th) -5V Source Follower Mode Output

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The discussion focuses on the operation of a PMOS FET in source follower mode with a gate-source voltage (Vgs) threshold of -5V. Hemant successfully demonstrates output from the PMOS when both the gate and source are connected to -5V, clarifying that the voltage is referenced to ground rather than the source. The conversation emphasizes the importance of understanding the voltage references in PMOS configurations for accurate circuit behavior.

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hemant03
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Hi,
I believe that to make a PMOS work, Vgs (th) needs to be negative but when I give -5V to source and connect it in a source follower mode i.e. vg = -5V, I do get an output.
Can anyone tell me how and why?

Thanks,
- Hemant
 
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1. Can you post a circuit diagram.

2. Can you make it clear whether you are using mosfets or jfets.
 
Last edited:
uart said:
1. Can you post a circuit diagram.

2. Can you make it clear whether you are using mosfets or jfets.

Hi,
I have attached a sample PMOS circuitry that I have simulated. I am actually using a PMOS FET.
 

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Thats because you shorted the gate and the source together. They are tied to -5 Volts with respect to ground but not -5 volts with respect to source.
 

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