Polled interrupts: how does the CPU know which ISR to run?

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In summary, interrupt handling can be done through either vectored interrupts or polled interrupts. In vectored interrupts, the device sends a specific code to the CPU to run a designated ISR. In polled interrupts, the CPU must determine which interrupt to run based on an interrupt register. Some CPUs only have a single interrupt vector, requiring the code to read the interrupt register to determine the appropriate ISR. Polling can also be used to simulate interrupts, but it requires careful planning and can be difficult for some programmers to understand. This method was used in the past for real-time code, such as in lightwave systems at Bell Labs.
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eliotsbowe
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Hello, may someone help me to understand this?
I know that in vectored interrupts, a device asks the CPU to run a certain ISR by sending a specific code. Now, in polled interrupts there's no interrupt vector. So how does the CPU know what's the Interrupt Service Routine to be run?
Perhaps there's only one Interrupt Service Routine per device? Or maybe each device can request one Routine per Interrupt Priority Level, so that the CPU knows what to do just by recognizing the device and the Priority Level of the request?



Thanks a lot for your help.
 
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  • #3
eliotsbowe said:
So how does the CPU know what's the Interrupt Service Routine to be run?
Depends on the CPU and the related hardware. Generally there will be an interrupt register to indicate which interrupts are pending. The interrrupt register could use a separate bit for each possible interrupt, or the hardware could have a priority encoder that returns a value representing the highest priority pending interrupt.

For polled interrupts, the CPU won't know which interrupt to run, instead the code will have to determine which interrupt to run based on the interrupt register contents. In addition, each interrupt handler may be keeping track of the "state" of a device, in order to decide which code segment should be used to handle the current interrupt as a device goes thorugh a series of states. In C, this can be done with a switch variable and switch / case statement or one or more pointers to functions and calls via those pointers to functions, where the switch variable or pointers to function are updated as the state of a device changes.

Even when using hardware interrupts, some CPUs, such as the ARM, only have a single interrupt vector (there's also another fast interrupt vector), so the code has to read an interrupt register to determine which routine to call even when using interrupts instead of polling.
 
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  • #4
got it, thanks!
 
  • #5
It is possible to simulate interrupts using "polling", which is basically a loop. Each time through the loop, the code looks down through a series of options and acts on the ones that need attention. When writing real-time code, polling has the advantage of allowing a programmer to know EXACTLY what the worst-case time for the loop will be. However, it takes a great deal of patience, planning and care to design.

I used to write code for lightwave systems at Bell Labs. Polling was the only way we could guarantee that everything would always get handled withing the required tolerances. But it was hard for some programmers to wrap their heads around it. We had about 5 different Motorola 68000 processors; they communicated with each other using shared memory, all by polling (no locking!). Each memory location could only be written by one processor, and the others could only read from that location. The readers would "debounce" (read multiple times, to see if changes occurred) before using new values.

The entire scheme was simple and did not involve operating system calls or hardware interrupts.
 

1. How does the CPU know when to execute an interrupt?

The CPU constantly checks for interrupt signals from various hardware devices. When an interrupt is received, the CPU suspends its current task and executes the Interrupt Service Routine (ISR) associated with that interrupt.

2. How does the CPU know which ISR to run?

Each interrupt is associated with a unique interrupt vector, which contains the memory address of the corresponding ISR. When an interrupt occurs, the CPU uses this vector to jump to the correct ISR.

3. Can multiple interrupts occur simultaneously?

Yes, multiple interrupts can occur simultaneously. The CPU prioritizes interrupts based on their urgency and executes the corresponding ISR based on the priority level.

4. What happens if an interrupt occurs while the CPU is already servicing another interrupt?

If a higher priority interrupt occurs while the CPU is servicing a lower priority interrupt, the CPU will suspend the lower priority interrupt and execute the ISR for the higher priority interrupt. Once the higher priority interrupt is completed, the CPU will resume servicing the lower priority interrupt.

5. What is the role of the Interrupt Service Routine (ISR) in polled interrupts?

In polled interrupts, the ISR is responsible for acknowledging the interrupt signal and clearing it so that the CPU can continue its normal execution. The ISR may also be responsible for handling any data or instructions related to the interrupt.

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